ZHCSO53G August   2010  – June 2021 TPD2EUSB30 , TPD2EUSB30A , TPD4EUSB30

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on D+, D- Pins
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-4D24F83F-9DF7-445D-8DDE-D3D0B2DA960E-low.gifFigure 5-1 DRT Package3-Pin SOTTop View
GUID-1B54AB68-3B54-4829-93B3-E268474648F2-low.gifFigure 5-2 DQA Package10-Pin USONTop View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME DRT DQA
D1+ 1 1 ESD port High-speed ESD clamp, provides ESD protection to the high-speed differential data lines.
D1– 2 2
D2+ — 4
D2– — 5
GND 3 3, 8 GND Ground
N.C. — 6, 7,
9, 10		 — Not normally connected