ZHCSDJ5B January   2015  – December 2017 TPA3140D2

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Gain Setting via GAIN Pin
      2. 9.3.2  SD Operation
      3. 9.3.3  Gain Limit Control, LIMTHRES and LIMRATE
      4. 9.3.4  SPEAKERGUARD Automatic Gain Limit, AGL
      5. 9.3.5  Thermal Foldback, TFB
      6. 9.3.6  PLIMIT
      7. 9.3.7  LIMTHRES
      8. 9.3.8  Spread Spectrum and De-Phase Control
      9. 9.3.9  GVDD Supply
      10. 9.3.10 DC Detect
      11. 9.3.11 PBTL Select
      12. 9.3.12 Short-Circuit Protection and Automatic Recovery Feature
      13. 9.3.13 Thermal Protection
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 PCB Material Recommendation
        2. 10.2.1.2 PVCC Capacitor Recommendation
        3. 10.2.1.3 Decoupling Capacitor Recommendations
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Ferrite Bead Filter Considerations
        2. 10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 10.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 10.2.2.4 Input Resistance
        5. 10.2.2.5 Input Capacitor, Ci
        6. 10.2.2.6 BSN and BSP Capacitors
        7. 10.2.2.7 Differential Inputs
        8. 10.2.2.8 Using Low-ESR Capacitors
      3. 10.2.3 Application Performance Curves
        1. 10.2.3.1 EN55013 Radiated Emissions Results
        2. 10.2.3.2 EN55022 Conducted Emissions Results
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling, CS
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 第三方产品免责声明
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP
(Top View)

Pin Functions

PIN I/O/P(1) DESCRIPTION
NAME NUMBER
SD 1 I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
FAULT 2 O Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling PVCC.
LINP 3 I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
LINN 4 I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
LIMRATE 5 I Decay speed for clip free power limiter. Connect a resistor divider from GVDD to GND to set decay speed. Connect directly to GND to disconnect limiter.
GAIN 6 I 4-state Amplifier gain select. Connect a resistor divider from GVDD to GND to set closed loop gain.
SSCTRL 7 I Spread spectrum control. Connect a resistor divider from GVDD to GND to set mode. Connect to GND for disable spread spectrum.
LIMTHRES 8 I Voltage limit level for AGL and power limiter. Connect a resistor divider from GVDD to GND to set limit. Connect directly to GVDD to disconnect limiter
GVDD 9 O High-side FET gate drive supply. Nominal voltage is 7 V. Also should be used as supply for LIMTHRES limit function
GND 10 P Analog signal ground.
RINN 11 I Negative audio input for right channel. Biased at 3 V.
RINP 12 I Positive audio input for right channel. Biased at 3 V.
1SPW 13 I Modulation scheme select. Low: BD mode, high: 1SPW mode.
AVCC 14 P Analog supply
PVCC 15 P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally.
PVCC 16 P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally.
BSPR 17 I Bootstrap I/O for right channel, positive high-side FET.
OUTPR 18 O Class-D H-bridge positive output for right channel.
GND 19 P Power ground for the H-bridges.
OUTNR 20 O Class-D H-bridge negative output for right channel.
BSNR 21 I Bootstrap I/O for right channel, negative high-side FET.
BSNL 22 I Bootstrap I/O for left channel, negative high-side FET.
OUTNL 23 O Class-D H-bridge negative output for left channel.
GND 24 P Power ground for the H-bridges.
OUTPL 25 O Class-D H-bridge positive output for left channel.
BSPL 26 I Bootstrap I/O for left channel, positive high-side FET.
PVCC 27 P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally.
PVCC 28 P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally.
Thermal Pad P Connect to GND for best thermal and electrical performance
(1) I = Input, O = Output, P = Power