ZHCSAA3B September   2012  – September 2015 TPA3112D1-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics
    6. 6.6 DC Characteristics
    7. 6.7 AC Characteristics
    8. 6.8 AC Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC Detect
      2. 7.3.2 Short-Circuit Protection and Automatic Recovery Feature
      3. 7.3.3 Thermal Protection
      4. 7.3.4 GVDD Supply
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gain Setting Through GAIN0 and GAIN1 Inputs
      2. 7.4.2 SD Operation
      3. 7.4.3 PLIMIT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Class-D Operation
        2. 8.2.2.2  TPA3112D1-Q1 Modulation Scheme
        3. 8.2.2.3  Ferrite Bead Filter Considerations
        4. 8.2.2.4  Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
        5. 8.2.2.5  When to Use an Output Filter for EMI Suppression
        6. 8.2.2.6  Input Resistance
        7. 8.2.2.7  Input Capacitor, CI
        8. 8.2.2.8  BSN and BSP Capacitors
        9. 8.2.2.9  Differential Inputs
        10. 8.2.2.10 Using Low-ESR Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP With PowerPAD™ IC
Top View
TPA3112D1-Q1 pinout_los618.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 SD I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
2 FAULT O Open drain output used to display short circuit or DC detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both the short circuit faults and DC detect faults must be reset by cycling PVCC.
3 GND — Connect to local ground.
4 GND — Connect to local ground.
5 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
6 GAIN1 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
7 AVCC P Analog supply
8 AGND — Analog supply ground. Connect to the thermal pad.
9 GVDD O High-side FET gate drive supply. Nominal voltage is 7 V. May also be used as supply for PLIMIT divider. Add a 1-μF cap to ground at this pin.
10 PLIMIT I Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1-μF cap to ground at this pin.
11 INN I Negative audio input. Biased at 3 V.
12 INP I Positive audio input. Biased at 3 V.
13 NC — Not connected
14 AVCC P Connect AVCC supply to this pin.
15 PVCC P Power supply for H-bridge. PVCC pins are also connected internally.
16 PVCC P Power supply for H-bridge. PVCC pins are also connected internally.
17 BSP I Bootstrap I/O for positive high-side FET.
18 OUTP O Class-D H-bridge positive output.
19 PGND — Power ground for the H-bridges.
20 OUTP O Class-D H-bridge positive output.
21 BSP I Bootstrap I/O for positive high-side FET.
22 BSN I Bootstrap I/O for negative high-side FET.
23 OUTN O Class-D H-bridge negative output.
24 PGND — Power ground for the H-bridges.
25 OUTN O Class-D H-bridge negative output.
26 BSN I Bootstrap I/O for negative high-side FET.
27 PVCC P Power supply for H-bridge. PVCC pins are also connected internally.
28 PVCC P Power supply for H-bridge. PVCC pins are also connected internally.