Place supply bypass capacitors as close to the VCC pin as possible. Avoid placing the bypass capacitors near the D+/D–traces. The high-speed D+/D– traces should always be matched and must be no more than 4 inches, otherwise the eye diagram performance may be degraded. A high-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic impedance. In the layout, the impedance of D+ and D– traces should match the cable characteristic differential impedance for optimal performance. Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended.

When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices, or IC’s that use or duplicate clock signals. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then the stub should be less than 200 mm. Route all high-speed USB signal traces over continuous planes (VCC or GND) with no interruptions. Avoid crossing over anti-etch, commonly found with plane split.

For high speed layout guidelines, refer to High-Speed Layout Guidelines for Signal Conditioners and USB Hubs application note.