ZHCSQ93B March   2022  – December 2023 TMUX7236

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Source or Drain Continuous Current
    6. 5.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 5.7  ±15 V Dual Supply: Switching Characteristics 
    8. 5.8  ±20 V Dual Supply: Electrical Characteristics
    9. 5.9  ±20 V Dual Supply: Switching Characteristics
    10. 5.10 44 V Single Supply: Electrical Characteristics 
    11. 5.11 44 V Single Supply: Switching Characteristics 
    12. 5.12 12 V Single Supply: Electrical Characteristics 
    13. 5.13 12 V Single Supply: Switching Characteristics 
    14. 5.14 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  Transition Time
    5. 6.5  tON(EN) and tOFF(EN)
    6. 6.6  Break-Before-Make
    7. 6.7  tON (VDD) Time
    8. 6.8  Propagation Delay
    9. 6.9  Charge Injection
    10. 6.10 Off Isolation
    11. 6.11 Crosstalk
    12. 6.12 Bandwidth
    13. 6.13 THD + Noise
    14. 6.14 Power Supply Rejection Ratio (PSRR)
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Bidirectional Operation
      2. 7.2.2 Rail to Rail Operation
      3. 7.2.3 1.8 V Logic Compatible Inputs
      4. 7.2.4 Integrated Pull-Down Resistor on Logic Pins
      5. 7.2.5 Fail-Safe Logic
      6. 7.2.6 Latch-Up Immune
      7. 7.2.7 Ultra-Low Charge Injection
    3. 7.3 Device Functional Modes
    4. 7.4 Truth Tables
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
        1. 8.2.3.1 On-Resistance Mismatch Between Channels
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 术语表
    6. 9.6 静电放电警告
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PW|16
  • RUM|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Pin Configuration and Functions

GUID-4F214FE3-25A2-4EB2-BAB1-4F613C7BA732-low.svgFigure 4-1 RUM Package,16-Pin WQFN(Top View)
GUID-20231116-SS0I-WJRH-SCX8-GZMKJJCP8NHX-low.svgFigure 4-2 PW Package,16-Pin TSSOP(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
D1 3 1 I/O Drain pin. Can be an input or output.
D2 11 9 I/O Drain pin. Can be an input or output.
GND 6 4 P Ground (0 V) reference
NC 7, 8, 15,16 5, 7, 13, 14 — No internal connection. Can be shorted to GND or left floating.
S1A 2 16 I/O Source pin 1A. Can be an input or output.
S1B 4 2 I/O Source pin 1B. Can be an input or output.
S2A 10 8 I/O Source pin 2A. Can be an input or output.
S2B 12 10 I/O Source pin 2B. Can be an input or output.
EN 14 12 I Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off. When this pin is high, the SEL logic input determine which switch is turned on.
SEL1 1 15 I Logic control input, has internal pull-down resistor. Controls the switch connection as shown in Section 7.4.
SEL2 9 6 I Logic control input, has internal pull-down resistor. Controls the switch connection as shown in Section 7.4.
VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VSS 5 3 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Thermal Pad — The thermal pad is not connected internally. There is no requirement to electrically connect this pad. If connected, however, it is recommended that the pad be left floating or tied to GND.
(1) I = input, O = output, P = power