ZHCSLR4F december   2019  – july 2023 TMUX1308-Q1 , TMUX1309-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TMUX1308-Q1
    5. 7.5  Thermal Information: TMUX1309-Q1
    6. 7.6  Electrical Characteristics
    7. 7.7  Logic and Dynamic Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Injection Current Coupling
    10. 7.10 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Transition Time
    5. 8.5  Break-Before-Make
    6. 8.6  tON(EN) and tOFF(EN)
    7. 8.7  Charge Injection
    8. 8.8  Off Isolation
    9. 8.9  Crosstalk
    10. 8.10 Bandwidth
    11. 8.11 Injection Current Control
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Rail-to-Rail Operation
      3. 9.3.3 1.8 V Logic Compatible Inputs
      4. 9.3.4 Fail-Safe Logic
      5. 9.3.5 Injection Current Control
        1. 9.3.5.1 TMUX13xx-Q1 is Powered, Channel is Unselected, and the Input Signal is Greater Than VDD (VDD = 5 V, VINPUT = 5.5 V)
        2. 9.3.5.2 TMUX13xx-Q1 is Powered, Channel is Selected, and the Input Signal is Greater Than VDD (VDD = 5 V, VINPUT = 5.5 V)
        3. 9.3.5.3 TMUX13xx-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0 V, VINPUT = 3 V)
    4. 9.4 Device Functional Modes
    5. 9.5 Truth Tables
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Short To Battery Protection
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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7.6 Electrical Characteristics

At specified VDD ±10%
Typical values measured at nominal VDD
PARAMETER TEST CONDITIONS VDD Operating free-air temperature (TA) UNIT
25°C –40°C to 85°C –40°C to 125°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
ANALOG SWITCH
RON On-state switch resistance VS = 0 V to VDD
ISD = 0.5 mA		 1.8 V 650 1500 1700 1700 Ω
2.5 V 230 600 670 670
3.3 V 120 330 350 370
5 V 75 195 220 270
ΔRON On-state switch resistance matching between inputs VS = VDD / 2 
ISD = 0.5 mA
 1.8 V 10 38 45 45 Ω
2.5 V 3 20 22 22
3.3 V 2 8 11 15
5 V 1 7 10 14
IS(OFF) Source off-state leakage current Switch Off
VD = 0.8 x VDD/ 0.2 x VDD
VS = 0.2 x VDD/ 0.8 x VDD		 1.8 V ±1 –25 25 –800 800 nA
2.5 V ±1 –25 25 –800 800
3.3 V ±1 –25 25 –800 800
5 V ±1 –25 25 –800 800
ID(OFF) Drain off-state leakage current (common drain pin) Switch Off
VD = 0.8 x VDD/ 0.2 x VDD
VS = 0.2 x VDD/ 0.8 x VDD		 1.8 V ±1 –45 45 –800 800 nA
2.5 V ±1 –45 45 –800 800
3.3 V ±1 –45 45 –800 800
5 V ±1 –45 45 –800 800
ID(ON)
IS(ON)		 Channel on-state leakage current Switch On
VD = VS = 0.8 x VDD or
VD = VS = 0.2 x VDD		 1.8 V ±1 –45 45 –800 800 nA
2.5 V ±1 –45 45 –800 800
3.3 V ±1 –45 45 –800 800
5 V ±1 –45 45 –800 800
CSOFF Source off capacitance VS = VDD / 2
f = 1 MHz		 1.8 V 2 14 14 14 pF
2.5 V 2 14 14 14
3.3 V 2 14 14 14
5 V 2 14 14 14
CDOFF Drain off capacitance VS = VDD / 2
f = 1 MHz		 1.8 V 7 37 37 37 pF
2.5 V 7 37 37 37
3.3 V 7 37 37 37
5 V 7 37 37 37
CSON
CDON		 On capacitance VS = VDD / 2
f = 1 MHz		 1.8 V 11 40 40 40 pF
2.5 V 11 40 40 40
3.3 V 11 40 40 40
5 V 11 40 40 40
POWER SUPPLY
IDD VDD supply current Logic inputs = 0 V or VDD 1.8 V 1 1 1.2 µA
2.5 V 1 1 1.5
3.3 V 1 1 2
5 V 1 1.5 3