ZHCSE08D May   2015  – January 2020 TMP107

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
    1.     Device Images
      1.      典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Temperature Limits and Alert
        1. 7.3.2.1 ALERT1, ALERT2, R1, and R2 Pins
      3. 7.3.3 SMAART Wire™ Communication Interface
        1. 7.3.3.1 Communication Protocol
          1. 7.3.3.1.1 Calibration Phase
          2. 7.3.3.1.2 Command and Address Phase
            1. 7.3.3.1.2.1 Global or Individual (G/nI) Bit
            2. 7.3.3.1.2.2 Read/Write (R/nW) Bit
            3. 7.3.3.1.2.3 Command or Address (C/nA) Bit:
          3. 7.3.3.1.3 Register Pointer Phase
          4. 7.3.3.1.4 Data Phase
        2. 7.3.3.2 SMAART Wire™ Operations
          1. 7.3.3.2.1 Command Operations
            1. 7.3.3.2.1.1 Address Initialize
            2. 7.3.3.2.1.2 Last Device Poll
            3. 7.3.3.2.1.3 Global Software Reset
          2. 7.3.3.2.2 Address Operations
            1. 7.3.3.2.2.1 Individual Write
            2. 7.3.3.2.2.2 Individual Read
            3. 7.3.3.2.2.3 Global Write
            4. 7.3.3.2.2.4 Global Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous-Conversion Mode
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
      1. 7.5.1 EEPROM
      2. 7.5.2 EEPROM Operations
        1. 7.5.2.1 EEPROM Unlock
        2. 7.5.2.2 EEPROM Lock
        3. 7.5.2.3 EEPROM Programming
        4. 7.5.2.4 EEPROM Acquire or Read
    6. 7.6 Register Map
      1. 7.6.1 Temperature Register (address = 0h) [reset = 0h]
        1. Table 4. Temperature Register Field Descriptions
      2. 7.6.2 Configuration Register (address = 1h) [reset = A000h]
        1. Table 5. Configuration Register Field Descriptions
      3. 7.6.3 High Limit 1 Register (address = 2h) [reset = 7FFCh]
        1. Table 7. High Limit 1 Register Field Descriptions
      4. 7.6.4 Low Limit 1 Register (address = 3h) [reset = 8000h]
        1. Table 8. Low Limit 1 Register Field Descriptions
      5. 7.6.5 High Limit 2 Register (address = 4h) [reset = 7FFCh]
        1. Table 9. High Limit 2 Register Field Descriptions
      6. 7.6.6 Low Limit 2 Register (address = 5h) [reset = 8000h]
        1. Table 10. Low Limit 2 Register Field Descriptions
      7. 7.6.7 EEPROM n Register (where n = 1 to 8) (addresses = 6h to Dh) [reset = 0h]
        1. Table 11. EEPROM Register bits
      8. 7.6.8 Die ID Register (address = Fh) [reset = 1107h]
        1. Table 12. Die ID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Connecting Multiple Devices
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Voltage Drop Effect
          2. 8.2.1.2.2 EEPROM Programming Current
          3. 8.2.1.2.3 Power Savings
          4. 8.2.1.2.4 Accuracy
          5. 8.2.1.2.5 Electromagnetic Interference (EMI)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Connecting ALERT1 and ALERT2 Pins
      3. 8.2.3 ALERT1 and ALERT2 Pins Used as General-Purpose Output (GPO)
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.2 Configuration Register (address = 1h) [reset = A000h]

The configuration register is a read and write register used to store bits that control the part operation. The format and power-up or reset value of the configuration register for the TMP107 is shown in Figure 32 and Table 5. When the NUS bit is 0, all writes to this register are stored in register logic. When NUS is 1, then all writes to this register program the EEPROM location that stores the configuration bits. Writes to this location are followed by a 16-ms wait period for programming the EEPROM. When the configuration register is written, the current conversion is aborted and new action is taken based on the new written bits. Thus, if the TMP107 is put into shutdown, the device goes into shutdown immediately. If the conversion rate is changed, any ongoing conversion is aborted and a new conversion starts with the new conversion rate.

Figure 32. Configuration Register
15 14 13 12 11 10 9 8
CR2 CR1 CR0 OS SD FH1 FL1 T1/A1
R/W-5h R/W-0h R/W-0h R-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
POL1 FH2 FL2 T2/A2 POL2 Reserved RST Reserved
R/W-0h R-0h R-0h R/W-0h R/W-0h R-0h W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 5. Configuration Register Field Descriptions

Bit Field Type Reset Description
15-13 CR2-CR0 R/W 5h Conversion rate.
The conversion rate bits control the update rate of the analog-to-digital converter (ADC). Table 6 describes the relationship between the values of the conversion rate bits and the corresponding conversion time and average quiescent current. These bits only affect continuous-conversion mode and not one-shot mode.
12 OS R/W 0h One-shot mode.
0: Default.
1: Starts a single temperature conversion if the SD bit is set to 1. The TMP107 returns to the shutdown state at the completion of the single conversion. When the configuration register is read, OS always reads zero.
11 SD R/W 0h Shutdown mode.
0: The TMP107 is in continuous-conversion mode.
1: The TMP107 is in shutdown mode. Initiate a conversion by writing a 1 to the OS bit.
10 FH1 R 0h High limit 1 flag.
0: Indicates that the temperature result does not exceed high limit 1.
1: Indicates when the temperature result exceeds high limit 1.
9 FL1 R 0h Low limit 1 flag. In therm mode, this bit is not used and always reads 0.
0: In alert mode, this bit indicates that the temperature result is greater than low limit 1.
1: In alert mode, this bit indicates when the temperature result is less than low limit 1.
8 T1/A1 R/W 0h Alert and therm mode 1.
0: Alert mode: In this mode, the high limit 1 and low limit 1 form a window. If the temperature result is greater than high limit 1 or less than low limit 1, the respective flag (either FH1 or FL1) is asserted. After the flag is asserted, clear the flag by reading the configuration register.
1: Therm mode: In this mode, the limits are used to form an upper limit threshold detector. If the temperature result is greater than high limit 1, the FH1 flag is asserted. The FH1 flag is then deasserted only after the temperature drops below low limit 1. In therm mode, only the FH1 flag is active. The FL1 flag always reads 0. In this mode, the flags are asserted and deasserted only at the end of a conversion and cannot be cleared by a configuration register read.
7 POL1 R/W 0h 0: Polarity of the ALERT1 pin is active low.
1: Polarity of the ALERT1 pin is active high.
6 FH2 R 0h High limit 2 flag.
0: Indicates that the temperature result does not exceed high limit 2.
1: Indicates when the temperature result exceeds high limit 2.
5 FL2 R 0h Low Limit 2 Flag. In therm mode, this bit is not used and always reads 0.
0: In alert mode, this bit indicates that the temperature result is greater than low limit 2.
1: In alert mode, this bit indicates when the temperature result is less than low limit 2.
4 T2/A2 R/W 0h Alert and therm mode 2.
0: Alert mode: in this mode, the high limit 2 and low limit 2 form a window. If the temperature result is greater than high limit 2 or less than low limit 2, the respective flag (either FH2 or FL2) is asserted. After the flag is asserted, clear the flag by reading the configuration register.
1: Therm mode: in this mode, the limits are used to form an upper limit threshold detector. If the temperature result is greater than high limit 2, the FH2 flag is asserted. The FH2 flag is then deasserted only after the temperature drops below low limit 2. In therm mode, only the FH2 flag is active. The FL2 flag always reads 0. In this mode, the flags are asserted and deasserted only at the end of a conversion and cannot be cleared by a configuration register read.
3 POL2 R/W 0h 0: Polarity of the ALERT2 pin is active low.
1: Polarity of the ALERT2 pin is active high.
2 Reserved R 0h Reserved
1 RST W 0h Software reset.
0: Default.
1: Reset. This bit is a write-only bit and is used to perform a software reset on the TMP107.
0 Reserved R/W 0h Reserved

Table 6. Conversion Rates

CR2 CR1 CR0 CONVERSION PERIOD CONVERSIONS PER SECOND AVERAGE IQ
(V+ = 3.3 V)
0 0 0 15 ms 62 200 µA
0 0 1 50 ms 20 20 µA
0 1 0 100 ms 10 15 µA
0 1 1 250 ms 4 11 µA
1 0 0 500 ms 2 9 µA
1 0 1 1 s (default) 1 (default) 7 µA
1 1 0 4 s 0.25 6 µA
1 1 1 16 s 0.0625 5 µA