ZHCSE91C September   2015  – June 2017 TL16C752D

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configurations and Function
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Functional Description
        1. 8.3.1.1  Trigger Levels
        2. 8.3.1.2  Hardware Flow Control
        3. 8.3.1.3  Auto-RTS
        4. 8.3.1.4  Auto-CTS
        5. 8.3.1.5  Software Flow Control
        6. 8.3.1.6  Software Flow Control Example
        7. 8.3.1.7  Reset
        8. 8.3.1.8  Interrupts
        9. 8.3.1.9  Interrupt Mode Operation
        10. 8.3.1.10 Polled Mode Operation
        11. 8.3.1.11 Break and Timeout Conditions
        12. 8.3.1.12 Programmable Baud Rate Generator
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMA Signaling
        1. 8.4.1.1 Single DMA Transfers (DMA Mode0 or FIFO Disable)
        2. 8.4.1.2 Block DMA Transfers (DMA Mode 1)
      2. 8.4.2 Sleep Mode
    5. 8.5 Register Maps
      1. 8.5.1  Principals of Operation
      2. 8.5.2  Receiver Holding Register (RHR)
      3. 8.5.3  Transmit Holding Register (THR)
      4. 8.5.4  FIFO Control Register (FCR)
      5. 8.5.5  Line Control Register (LCR)
      6. 8.5.6  Line Status Register (LSR)
      7. 8.5.7  Modem Control Register (MCR)
      8. 8.5.8  Modem Status Register (MSR)
      9. 8.5.9  Interrupt Enable Register (IER)
      10. 8.5.10 Interrupt Identification Register (IIR)
      11. 8.5.11 Enhanced Feature Register (EFR)
      12. 8.5.12 Divisor Latches (DLL, DLH)
      13. 8.5.13 Transmission Control Register (TCR)
      14. 8.5.14 Trigger Level Register (TLR)
      15. 8.5.15 FIFO Ready Register
      16. 8.5.16 Alternate Function Register (AFR)
      17. 8.5.17 RS-485 Mode
      18. 8.5.18 IrDA Overview
      19. 8.5.19 IrDA Encoder Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12器件和文档支持
    1. 12.1 社区资源
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configurations and Function

PFB Package
48-Pin TQFP
Top View
TL16C752D po_pfb_lls646.gif
N.C. – No internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME TQFP
A0 28 I Address bit 0 select. Internal registers address selection. Refer to Figure 26 for register address map.
A1 27 I Address bit 1 select. Internal registers address selection. Refer to Figure 26 for register address map.
A2 26 I Address bit 2 select. Internal registers address selection. Refer to Figure 26 for register address map.
CDA, CDB 40, 16 I Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has been detected by the modem for that channel.
CSA, CSB 10, 11 I Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752D for the channel or channels addressed. Individual UART sections (A and B) are addressed by providing a low on the respective CSA and CSB pin.
CTSA, CTSB 38, 23 I Clear to send (active low). These inputs are associated with individual UART channels A and B. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the TL16C752D device. Status can be checked by reading MSR[4]. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR[7]), for hardware flow control operation.
D0–D4,
D5–D7		 44 to 48,
1 to 3 		I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.
DSRA, DSRB 39, 20 I Data set ready (active low). These inputs are associated with individual UART channels A through B. A low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART.
DTRA, DTRB 34, 35 O Data terminal ready (active low). These outputs are associated with individual UART channels A through B. A low on these pins indicates that the TL16C752D is powered on and ready. These pins can be controlled through the modem control register. Writing a 1 to MCR[0] sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR[0], or after a reset. These pins can also be used in the RS-485 mode to control an external RS-485 driver or transceiver.
GND 17 Pwr Power signal and power ground
INTA, INTB 30, 29 O Interrupt A and B (active high). These pins provide individual channel interrupts, INTA-B. INTA-B are enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt enable register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. INTA-B are in the high-impedance state after reset.
IOR 19 I Read input (active low strobe). A valid low level on IOR loads the contents of an internal register defined by address bits A0 through A2 onto the TL16C752D device data bus (D0 through D7) for access by an external CPU.
IOW 15 I Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0 through D7) from the external CPU to an internal register that is defined by address bits A0 through A2.
NC 12, 24,
37		 No internal connection
OPA, OPB 32, 9 O User defined outputs. This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins is high after reset.
RESET 36 I Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the receiver input are disabled during reset time. For initialization details, see TL16C752D device external reset conditions. RESET is an active high input.
RIA, RIB, 41, 21 I Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem has received a ringing signal from the telephone line. A low-to-high transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR).
RTSA, RTSB 33, 22 O Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the RTS pins indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control register (MCR[1]) sets these pins to low, indicating data is available. After a reset, these pins are set to 1. These pins only affect the transmit and receive operation when auto-RTS function is enabled through the enhanced feature register (EFR[6]), for hardware flow control operation.
RXA, RXB 5, 4 I Receive data input. These inputs are associated with individual serial channel data to the TL16C752D device. During the local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX input internally. During normal mode, RXn should be held high when no data is being received. These inputs also can be used in IrDA mode. For more information, see IrDA Overview.
RXRDYA,
RXRDYB 		31, 18 O Receive ready (active low). RXRDYA and RXRDYB go low when the trigger level has been reached or a timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.
TXA, TXB, 7, 8 O Transmit data. These outputs are associated with individual serial transmit channel data from the TL16C752D device. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.
TXRDYA,
TXRDYB 		43, 6 O Transmit ready (active low). TXRDYA and TXRDYB go low when there are a trigger level number of spares available. They go high when the TX buffer is full.
VCC 42 PWR Power supply inputs
XTAL1 13 I Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 23). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
XTAL2 14 O Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output or buffered clock output.