ZHCSJ48F December 2016 – December 2018 TDA2P-ABZ
ADVANCE INFORMATION for pre-production products; subject to change without notice.
For more information, see Power, Reset and Clock Management / PRCM Subsystem Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements section of the Device TRM.
The index numbers 1 and 2 which is part of the EMIF1 and EMIF2 signal prefixes (ddr1_* and ddr2_*) listed in Table 4-5, EMIF Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 and DDR2 types of SDRAM memories.
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is still present in some clock or DPLL names.
All IO cells are NOT Fail-safe compliant and should not be externally driven in absence of their IO supply.