ZHCSP69E August   2009  – May 2022 TCA9535

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Tolerant I/O Ports
      2. 7.3.2 Hardware Address Pins
      3. 7.3.3 Interrupt ( INT) Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Powered-Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 Bus Transactions
          1. 7.5.1.1.1 Writes
          2. 7.5.1.1.2 Reads
      2. 7.5.2 Device Address
      3. 7.5.3 Control Register and Command Byte
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 8.2.1.2 Minimizing ICC When I/O is Used to Control LED
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.5.1.1.1 Writes

To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as well as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the controller then sends the register address of the register to which it wishes to write. The target acknowledges again, letting the controller know it is ready. After this, the controller starts sending the register data to the target until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller terminates the transmission with a STOP condition.

See the Control Register and Command Byte section to see list of the TCA9535 internal registers and a description of each one.

Figure 7-5 shows an example of writing a single byte to a target register.

GUID-41CC0920-1AFE-4C89-ADC4-21FC0798FEF1-low.gif Figure 7-5 Write to Register

Figure 7-6 shows the Write to the Polarity Inversion Register.

GUID-20211028-SS0I-9Q0F-MSVF-JK9RPBBG5HXP-low.gif Figure 7-6 Write to the Polarity Inversion Register

Figure 7-7 shows the Write to Output Port Registers.

GUID-20211028-SS0I-PC0N-MQN6-KXCZ4JQXWHT5-low.gif Figure 7-7 Write to Output Port Registers