ZHCSLQ0B August   2020  – November 2023 TCA4307

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hot bus insertion
      2. 7.3.2 Pre-charge voltage
      3. 7.3.3 Rise time accelerators
      4. 7.3.4 Bus ready output indicator
      5. 7.3.5 Powered-off high impedance for I2C and I/O pins
      6. 7.3.6 Supports clock stretching and arbitration
      7. 7.3.7 Stuck bus recovery
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-up and precharge
      2. 7.4.2 Bus idle
      3. 7.4.3 Bus active
      4. 7.4.4 Bus stuck
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Series connections
        2. 8.2.1.2 Multiple connections to a common node
        3. 8.2.1.3 Propagation delays
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application on a Backplane
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Best Practices
      2. 8.3.2 Power-on Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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5.6 Timing Requirements

MIN NOM MAX UNIT
fSCL_MAX Maximum SCL clock frequency 400 kHz
tBUF(1) Bus free time between a STOP and START condition 1.3 µs
tHD;STA(1) Hold time for a repeated START condition 0.6 µs
tSU;STA(1) Set-up time for a repeated START condition 0.6 µs
tSU;STO(1) Set-up time for a STOP condition 0.6 µs
tHD;DAT(1) Data hold time 0 ns
tSU;DAT(1) Data set-up time 100 ns
tLOW(1) LOW period of the SCL clock 1.3 µs
tHIGH(1) HIGH period of the SCL clock 0.6 µs
tf(1) Fall time of both SDA and SCL signals 20 × (VCC/5.5 V) 300 ns
tr(1) Rise time of both SDA and SCL signals 20 × (VCC/5.5 V) 300 ns
(1) These are system-level timing specs and are dependent upon bus capacitance and pull up resistor value. It is up to the system designer to ensure they are met