ZHCSLQ0B August   2020  – November 2023 TCA4307

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hot bus insertion
      2. 7.3.2 Pre-charge voltage
      3. 7.3.3 Rise time accelerators
      4. 7.3.4 Bus ready output indicator
      5. 7.3.5 Powered-off high impedance for I2C and I/O pins
      6. 7.3.6 Supports clock stretching and arbitration
      7. 7.3.7 Stuck bus recovery
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-up and precharge
      2. 7.4.2 Bus idle
      3. 7.4.3 Bus active
      4. 7.4.4 Bus stuck
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Series connections
        2. 8.2.1.2 Multiple connections to a common node
        3. 8.2.1.3 Propagation delays
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application on a Backplane
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Best Practices
      2. 8.3.2 Power-on Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

GUID-1BFC113E-E9DA-4F9D-BB2C-77D428D6C323-low.gifFigure 4-1 8-Pin VSSOP, DGK Package
(Top View)
Figure 4-2 8-Pin WSON, DRG Package
(Top View)
PIN TYPE DESCRIPTION
NAME NO.
EN 1 I Active-high chip enable pin. If EN is low, the TCA4307 is in a low current mode. It also disables the rise-time accelerators, disables the bus pre-charge circuitry, drives READY low, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. EN should be high (at VCC) for normal operation. Connect EN to VCC if this feature is not being used.
SCLOUT 2 I/O Serial clock output. Connect this pin to the SCL bus on the card.
SCLIN 3 I/O Serial clock input. Connect this pin to the SCL bus on the backplane.
GND 4 - Supply ground
READY 5 O Connection flag/rise-time accelerator control. Ready is low when either EN is low or the start-up sequence has not been completed. READY goes high when EN is high and start-up is complete. Connect a 10-kΩ resistor from this pin to VCC to provide the pull-up current.
SDAIN 6 I/O Serial data input. Connect this pin to the SDA bus on the backplane.
SDAOUT 7 I/O Serial data output. Connect this pin to the SDA bus on the card.
VCC 8 - Supply Power. Main input power supply from backplane. This is the supply voltage for the devices on the backplane I2C buses. Connect pull-up resistors from SDAIN and SCLIN (and also from SDAOUT and SCLOUT) to this supply. It is recommended to place a bypass capacitor of 0.1 μF close to this pin for best results.