ZHCST08A December 2022 – September 2023 TAS6424R-Q1
PRODUCTION DATA
The Mode Control register is shown in Figure 9-14 and described in Table 9-10.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESET | RESERVED | PBTL CH34 | PBTL CH12 | CH1 LO MODE | CH2 LO MODE | CH3 LO MODE | CH4 LO MODE |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESET | R/W | 0 | 0: Normal operation 1: Resets the device. Self-clearing, reads back 0. |
| 6 | RESERVED | R/W | 0 | RESERVED |
| 5 | PBTL CH34 | R/W | 0 | 0: Channels 3 and 4 are in BTL mode 1: Channels 3 and 4 are in parallel BTL mode |
| 4 | PBTL CH12 | R/W | 0 | 0: Channels 1 and 2 are in BTL mode 1: Channels 1 and 2 are in parallel BTL mode |
| 3 | CH1 LO MODE | R/W | 0 | 0: Channel 1 is in normal/speaker mode 1: Channel 1 is in line output mode |
| 2 | CH2 LO MODE | R/W | 0 | 0: Channel 2 is in normal/speaker mode 1: Channel 2 is in line output mode |
| 1 | CH3 LO MODE | R/W | 0 | 1: Channel 3 is in line output mode |
| 0 | CH4 LO MODE | R/W | 0 | 1: Channel 4 is in line output mode |