ZHCSH30C August 2017 – April 2018 TAS5755M
PRODUCTION DATA.
SUBADDRESS | REGISTER NAME | NO. OF BYTES | CONTENTS(1) | INITIALIZATION VALUE |
---|---|---|---|---|
0x00 | Clock control register | 1 | Description shown in subsequent section | 0x6C |
0x01 | Device ID register | 1 | Description shown in subsequent section | 0x00 |
0x02 | Error status register | 1 | Description shown in subsequent section | 0x00 |
0x03 | System control register 1 | 1 | Description shown in subsequent section | 0xA0 |
0x04 | Serial data interface register | 1 | Description shown in subsequent section | 0x05 |
0x05 | System control register 2 | 1 | Description shown in subsequent section | 0x40 |
0x06 | Soft mute register | 1 | Description shown in subsequent section | 0x00 |
0x07 | Master volume | 1 | Description shown in subsequent section | 0xFF (mute) |
0x08 | Channel 1 vol | 1 | Description shown in subsequent section | 0x30 (0 dB) |
0x09 | Channel 2 vol | 1 | Description shown in subsequent section | 0x30 (0 dB) |
0x0A | Channel 3 vol | 1 | Description shown in subsequent section | 0x30 (0 dB) |
0x0B–0x0D | 1 | Reserved(2) | ||
0x0E | Volume configuration register | 1 | Description shown in subsequent section | 0x91 |
0x0F | 1 | Reserved(2) | ||
0x10 | Modulation limit register | 1 | Description shown in subsequent section | 0x02 |
0x11 | IC delay channel 1 | 1 | Description shown in subsequent section | 0xAC |
0x12 | IC delay channel 2 | 1 | Description shown in subsequent section | 0x54 |
0x13 | IC delay channel 3 | 1 | Description shown in subsequent section | 0xAC |
0x14 | IC delay channel 4 | 1 | Description shown in subsequent section | 0x54 |
0x15-0x18 | 1 | Reserved(2) | ||
0x19 | PWM channel shutdown group register | 1 | Description shown in subsequent section | 0x30 |
0x1A | Start/stop period register | 1 | 0x0F | |
0x1B | Oscillator trim register | 1 | 0x82 | |
0x1C | BKND_ERR register | 1 | 0x02 | |
0x1D–0x1F | 1 | Reserved(2) | ||
0x20 | Input MUX register | 4 | Description shown in subsequent section | 0x0001 7772 |
0x21 | Ch 4 source select register | 4 | Description shown in subsequent section | 0x0000 4303 |
0x22 -0x24 | 4 | Reserved(2) | ||
0x25 | PWM MUX register | 4 | Description shown in subsequent section | 0x0102 1345 |
0x26-0x28 | 4 | Reserved(2) | ||
0x29 | ch1_bq[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2A | ch1_bq[1] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2B | ch1_bq[2] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2C | ch1_bq[3] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2D | ch1_bq[4] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2E | ch1_bq[5] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2F | ch1_bq[6] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x30 | ch2_bq[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x31 | ch2_bq[1] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x32 | ch2_bq[2] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x33 | ch2_bq[3] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x34 | ch2_bq[4] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x35 | ch2_bq[5] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x36 | ch2_bq[6] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x37 - 0x39 | 4 | Reserved(2) | ||
0x3A | DRC1 ae(3) | 8 | u[31:26], ae[25:0] | 0x0080 0000 |
DRC1 (1 – ae) | u[31:26], (1 – ae)[25:0] | 0x0000 0000 | ||
0x3B | DRC1 aa | 8 | u[31:26], aa[25:0] | 0x0080 0000 |
DRC1 (1 – aa) | u[31:26], (1 – aa)[25:0] | 0x0000 0000 | ||
0x3C | DRC1 ad | 8 | u[31:26], ad[25:0] | 0x0080 0000 |
DRC1 (1 – ad) | u[31:26], (1 – ad)[25:0] | 0x0000 0000 | ||
0x3D | DRC2 ae | 8 | u[31:26], ae[25:0] | 0x0080 0000 |
DRC 2 (1 – ae) | u[31:26], (1 – ae)[25:0] | 0x0000 0000 | ||
0x3E | DRC2 aa | 8 | u[31:26], aa[25:0] | 0x0080 0000 |
DRC2 (1 – aa) | u[31:26], (1 – aa)[25:0] | 0x0000 0000 | ||
0x3F | DRC2 ad | 8 | u[31:26], ad[25:0] | 0x0080 0000 |
DRC2 (1 – ad) | u[31:26], (1 – ad)[25:0] | 0x0000 0000 | ||
0x40 | DRC1-T | 4 | T1[31:0] (9.23 format) | 0xFDA2 1490 |
0x41 | DRC1-K | 4 | u[31:26], K1[25:0] | 0x0384 2109 |
0x42 | DRC1-O | 4 | u[31:26], O1[25:0] | 0x0008 4210 |
0x43 | DRC2-T | 4 | T2[31:0] (9.23 format) | 0xFDA2 1490 |
0x44 | DRC2-K | 4 | u[31:26], K2[25:0] | 0x0384 2109 |
0x45 | DRC2-O | 4 | u[31:26], O2[25:0] | 0x0008 4210 |
0x46 | DRC control | 4 | Description shown in subsequent section | 0x0000 0000 |
0x47–0x4F | 4 | Reserved(2) | ||
0x50 | Bank switch control | 4 | Description shown in subsequent section | 0x0F70 8000 |
0x51 | Ch 1 output mixer | 12 | Ch 1 output mix1[2] | 0x0080 0000 |
Ch 1 output mix1[1] | 0x0000 0000 | |||
Ch 1 output mix1[0] | 0x0000 0000 | |||
0x52 | Ch 2 output mixer | 12 | Ch 2 output mix2[2] | 0x0080 0000 |
Ch 2 output mix2[1] | 0x0000 0000 | |||
Ch 2 output mix2[0] | 0x0000 0000 | |||
0x53 | Ch 1 input mixer | 16 | Ch 1 input mixer[3] | 0x0080 0000 |
Ch 1 input mixer[2] | 0x0000 0000 | |||
Ch 1 input mixer[1] | 0x0000 0000 | |||
Ch 1 input mixer[0] | 0x0080 0000 | |||
0x54 | Ch 2 input mixer | 16 | Ch 2 input mixer[3] | 0x0080 0000 |
Ch 2 input mixer[2] | 0x0000 0000 | |||
Ch 2 input mixer[1] | 0x0000 0000 | |||
Ch 2 input mixer[0] | 0x0080 0000 | |||
0x55 | Channel 3 input mixer | 12 | Channel 3 input mixer [2] | 0x0080 0000 |
Channel 3 input mixer [1] | 0x0000 0000 | |||
Channel 3 input mixer [0] | 0x0000 0000 | |||
0x56 | Output post-scale | 4 | u[31:26], post[25:0] | 0x0080 0000 |
0x57 | Output pre-scale | 4 | u[31:26], pre[25:0] (9.17 format) | 0x0002 0000 |
0x58 | ch1 BQ[7] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x59 | ch1 BQ[8] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5A | Subchannel BQ[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5B | Subchannel BQ[1] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5C | ch2 BQ[7] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5D | ch2 BQ[8] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5E | pseudo_ch2 BQ[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5F | 4 | Reserved(2) | ||
0x60 | Channel 4 (subchannel) output mixer | 8 | Ch 4 output mixer[1] | 0x0000 0000 |
Ch 4 output mixer[0] | 0x0080 0000 | |||
0x61 | Channel 4 (subchannel) input mixer | 8 | Ch 4 input mixer[1] | 0x0040 0000 |
Ch 4 input mixer[0] | 0x0040 0000 | |||
0x62 | IDF post scale | 4 | Post-IDF attenuation register | 0x0000 0080 |
0x63–0xF7 | Reserved(2) | 0x0000 0000 | ||
0xF8 | Device address enable register | 4 | Write F9 A5 A5 A5 in this register to enable write to device address update (0xF9) | 0x0000 0000 |
0xF9 | Device address Update Register | 4 | u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id (7:1) defines the new device address | 0X0000 0036 |
0xFA–0xFF | 4 | Reserved(2) | 0x0000 0000 |
All DAP coefficients are 3.23 format unless specified otherwise.