ZHCSJ32C December   2018  – September 2020 SN74AXCH1T45

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics: TA = 25°C
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Standard CMOS Inputs
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation
      5. 8.3.5 Over-voltage Tolerant Inputs
      6. 8.3.6 Negative Clamping Diodes
      7. 8.3.7 Fully Configurable Dual-Rail Design
      8. 8.3.8 Supports High-Speed Translation
      9. 8.3.9 Bus-Hold Data Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Enable Times
    2. 9.2 Typical Applications
      1. 9.2.1 Interrupt Request Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Universal Asynchronous Receiver-Transmitter (UART) Interface Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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6.6 Operating Characteristics: TA = 25°C

PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT
CpdA Power Dissipation Capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 2.0 pF
0.8 V 0.8 V 2.0
0.9 V 0.9 V 2.0
1.2 V 1.2 V 2.0
1.5 V 1.5 V 1.9
1.8 V 1.8 V 2.0
2.5 V 2.5 V 2.4
3.3 V 3.3 V 3.0
Power Dissipation Capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 12 pF
0.8 V 0.8 V 12
0.9 V 0.9 V 12
1.2 V 1.2 V 12
1.5 V 1.5 V 13
1.8 V 1.8 V 13
2.5 V 2.5 V 17
3.3 V 3.3 V 21
CpdB Power Dissipation Capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 12 pF
0.8 V 0.8 V 12
0.9 V 0.9 V 12
1.2 V 1.2 V 12
1.5 V 1.5 V 13
1.8 V 1.8 V 13
2.5 V 2.5 V 17
3.3 V 3.3 V 21
Power Dissipation Capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 2.1 pF
0.8 V 0.8 V 2.2
0.9 V 0.9 V 2.2
1.2 V 1.2 V 2.2
1.5 V 1.5 V 2.3
1.8 V 1.8 V 2.3
2.5 V 2.5 V 2.6
3.3 V 3.3 V 3.3