ZHCSMQ8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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6.3 Recommended Operating Conditions

see (1)
MINNOMMAXUNIT
VDDSupply voltages1.651.81.95V
VDDPLLA
VDDPLLD
VDDLVDS
VDDn(PP)Supply voltage noise magnitude 50 MHz (all supplies)Test set-up see Figure 7-1mV
fCLK ≤ 50 MHz; f(noise) = 1 Hz to 2 GHz100
fCLK > 50 MHz; f(noise) = 1 Hz to 1 MHz100
fCLK > 50 MHz; f(noise) > 1 MHz40
TAOperating free-air temperature–4085°C
CLK+ and CLK–
fCLK±Input Pixel clock frequency1-Channel receive mode, see Figure 8-4415MHz
2-Channel receive mode, see Figure 8-5830
3-Channel receive mode, see Figure 8-62065
Standby mode(2), see Figure 7-10500kHz
tDUTCLKCLK Input Duty Cycle35%65%
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
|VID|Magnitude of differential input voltage|VD0+ – VD0–|, |VD1+ – VD1–|, |VD2+ – VD2–|,
|VCLK+ – VCLK–| during normal operation		70200mV
VICMInput voltage common mode rangeReceive or Acquire mode0.61.2V
Stand-by mode0.9 × VDDLVDS
ΔVICMInput voltage common mode variation between all SubLVDS inputsVICM(n) – VICM(m) with
n = {D0, D1, D2, or CLK} and
m = {D0, D1, D2, or CLK}		–100100mV
ΔVIDDifferential input voltage amplitude variation between all SubLVDS inputsVID(n) – VID(m) with
n = {D0, D1, D2, or CLK} and
m = {D0, D1, D2, or CLK}		–10%10%
tR/FInput rise and fall timeRXEN at VDD; see figure 10800ps
ΔtR/FInput rise or fall time mismatch between all SubLVDS inputstR(n) – tR(m) and tF(n) – tF(m) with
n = {D0, D1, D2, or CLK} and
m = {D0, D1, D2, or CLK}		–100100ps
LS0, LS1, CPOL, SWAP, RXEN, F/S
VICMOSHHigh-level input voltage0.7 × VDDVDDV
VICMOSLLow-level input voltage00.3 × VDDV
tinRXENRXEN input pulse duration10μs
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
CLOutput load capacitance10pF
(1) Unused single-ended inputs must be held high or low to prevent them from floating.
(2) PCLK input frequencies lower than 500 kHz forces the SN65LVDS302 into standby mode. Input frequencies from 500 kHz to 3 MHz may or may not activate the SN65LVDS302. Input frequencies beyond 3 MHz activate the SN65LVDS302. TI recommends against input frequencies from 500 kHz to 4 MHz, which can cause PLL malfunction.