| PARAMETER | TEST CONDITIONS | MIN | UNIT |
|---|
| tRSKMx(2)(3) | Receiver input skew margin(1) (see Figure 9-2) | 1ChM: x = 0.29, fPCLK = 15 MHz,
RXEN at VDD, VIH = VDD, VIL = GND,
RL = 100 Ω, test setup as in Figure 7-2,
test pattern as in Table 7-7 | fCLK = 15 MHz(4) | 630 | ps |
| fCLK = 4 MHz to 15 MHz(5) | 1 / (60 × fCLK) – 480 |
2ChM: x = 0.14, fPCLK = 30 MHz,
RXEN at VDD, VIH = VDD, VIL = GND,
RL = 100 Ω, test setup as in Figure 7-2,
test pattern as in Table 7-8 | fCLK = 30 MHz(4) | 630 |
| fCLK = 8 MHz to 30 MHz(5) | 1 / (30 × fCLK) – 480 |
3ChM: RXEN at VDD, VIH = VDD, VIL = GND,
test setup as in Figure 7-2,
test pattern as in Table 7-9 | fCLK = 65 MHz(4) | 360 |
| fCLK = 20 MHz to 65 MHz(5) | 1 / (20 × fCLK) – 410 |
(1) This includes the receiver internal set-up and hold time uncertainty, all PLL related high-frequency random and deterministic jitter components that impact the jitter budget, ISI and duty cycle distortion from the front end receiver, and the skew from CLK to data D0, D1, and D2; The pulse position minimum and maximum variation is given with a bit error rate target of 10–12; Measurements of the total jitter are taken over a sample amount of > 10–12 samples.
(2) Receiver Input Skew Margin (tRSKM) is the timing margin available for transmitter output pulse position (tPPOS), interconnect skew, and interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe uncertainty;. The tRSKM assumes a bit error rate better than 10-12.
(3) tRSKM is indirectly proportional to the internal set-up and hold time uncertainty, ISI and duty cycle distortion from the front end receiver, the skew mismatch from CLK to data D0, D1, and D2, as well as the PLL cycle-to-cycle jitter.
(4) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
(5) These Minimum and Maximum Limits are simulated only.