ZHCSMQ8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
While LS0 and LS1 are held low, the SN65LVDS302 receives payload data over a single SubLVDS data pair, D0. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 30. The internal high speed clock is used to shift in the data payload on D0 and to deserialize 30 bits of data. Figure 8-4 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided by a factor of 30 to recreate the pixel clock and the data payload with the pixel clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode, the PLL can lock to a clock that is in the range of 4 MHz through 15 MHz. This mode is intended for smaller video display formats that do not need the full bandwidth capabilities of the SN65LVDS302.