SLLS804D March   2009  – August 2016 SN65HVDA540-5-Q1 , SN65HVDA540-Q1 , SN65HVDA541-5-Q1 , SN65HVDA541-Q1 , SN65HVDA542-5-Q1 , SN65HVDA542-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Ratings
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs and Outputs
      2. 8.3.2 TXD Dominant State Time Out
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Undervoltage Lockout and Unpowered Device
      5. 8.3.5 Floating Pins
      6. 8.3.6 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Bus States by Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode (HVDA540)
      4. 8.4.4 Standby Mode With RXD Wake Up-Request (HVDA541)
        1. 8.4.4.1 RXD Wake Up Request Lock Out for Bus Stuck Dominant Fault (HVDA541)
      5. 8.4.5 Silent (Receive Only) Mode (HVDA542)
      6. 8.4.6 Driver and Receiver Function Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V I/O Voltage Level and Normal Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Loop Propagation Delay
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VCC Supply voltage –0.3 6 V
VIO I/O supply voltage –0.3 6 V
Voltage at bus terminals (CANH, CANL) –27 40 V
IO Receiver output current (RXD) 20 mA
VI Voltage input (TXD, STB, S) HVDA54x –0.3 6 V and VI ≤ VIO + 0.3 V
HVDA54x-5 –0.3 6 V
TJ Operating virtual-junction temperature –40 150 °C
TLEAD Lead temperature (soldering, 10 seconds) 260 °C
Tstg Storage temperature °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) All pins except 6 and 7 ±4000 V
Pins 6 and 7(2) ±12000
Charged-device model (CDM), per AEC Q100-011 ±1000
Machine model ±7000
IEC 61000-4-2 contact discharge(3) Pins 6 and 7 to pin 2 ±7000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) HBM test method based on AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND.
(3) IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system level configurations will lead to different results.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 4.68 5.33 V
VIO I/O supply voltage 3 5.33 V
VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V
VIH High-level input voltage TXD, STB, S (for HVD54x-5: VIO = VCC) 0.7 × VIO VIO V
VIL Low-level input voltage TXD, STB, S (for HVD54x-5: VIO = VCC) 0 0.3 × VIO V
VID Differential input voltage, bus Between CANH and CANL –6 6 V
IOH High-level output current RXD –2 mA
IOL Low-level output current RXD 2 mA
TA Operating ambient free-air temperature See Thermal Information and Power Dissipation Ratings –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) HVDA54x, HVDA54x-5-Q1 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance Low-K thermal resistance 140 °C/W
High-K thermal resistance 112
RθJC(top) Junction-to-case (top) thermal resistance 56 °C/W
RθJB Junction-to-board thermal resistance 50 °C/W
ψJT Junction-to-top characterization parameter 13 °C/W
ψJB Junction-to-board characterization parameter 55 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices VIO = VCC
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SUPPLY CHARACTERISTICS (HVDA54x)
ICC 5-V supply current Standby mode (HVDA540/541 Only) STB at VIO, VCC = 5.33 V, VIO = 3 V, TXD at VIO (2) 5 µA
Normal mode (Dominant) TXD at 0 V, 60-Ω load, STB / S at 0 V 50 70 mA
Normal mode (Recessive) TXD at VIO, No load, STB / S at 0 V or S at VIO 5.5 10
Silent Mode (HVDA542 only) TXD at VIO, No load, STB / S at 0 V or S at VIO 5.5 10
IIO I/O supply current Standby mode (HVDA540/541 Only) STB at VIO , VCC = 5.33 V or 0 V, RXD floating, TXD at VIO
TA = –40°C, 25°C, 125°C(3)		 7 15 µA
Normal mode (recessive or dominant) and Silent Mode (HVDA542 Only) VCC = 5.33 V, RXD floating, TXD at 0 V or VIO. Normal Mode: STB or S at 0 V. Silent Mode (HVDA542): S at VIO. 75 300
UVVCC Undervoltage detection on VCC for forced standby mode 3.2 3.6 4 V
VHYS(UVVCC) Hysteresis voltage for undervoltage detection on UVVCC for standby mode 200 mV
UVVIO Undervoltage detection on VIO for forced standby mode 1.9 2.45 2.95 V
VHYS(UVVIO) Hysteresis voltage for undervoltage detection on UVVIO for forced standby mode 130 mV
SUPPLY CHARACTERISTICS (HVDA54x-5)
ICC 5-V supply current Standby mode (HVDA540-5/541-5 Only) STB at VCC, VCC = 5.33 V, TXD at VCC (2) 20 µA
Normal mode (Dominant) TXD at 0 V, 60-Ω load, STB / S at 0 V 50 70 mA
Normal mode (Recessive) TXD at VIO, No load, STB / S at 0 V or S at VIO 5.5 10
Silent Mode (HVDA542 only) TXD at VIO, No load, STB / S at 0 V or S at VIO 5.5 10
UVVCC Undervoltage detection on VCC for forced standby mode 3.2 3.6 4 V
VHYS(UVVCC) Hysteresis voltage for undervoltage detection on UVVCC for standby mode 240 mV
DEVICE SWITCHING CHARACTERISTICS: PROPAGATION TIME (LOOP TIME TXD TO RXD)
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant Figure 9, STB at 0 V 70 230 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 70 230
DRIVER ELECTRICAL CHARACTERISTICS
VO(D) Bus output voltage (dominant) CANH VI = 0 V, STB / S at 0 V, RL = 60 Ω,
See Figure 2 and Figure 15 		2.9 4.5 V
CANL 0.8 1.75
VO(R) Bus output voltage (recessive) VI = VIO, VIO = 3 V, STB at 0 V or S at X(4), RL = 60 Ω, See Figure 2 and Figure 15 2 2.5 3 V
VO(STBY) Bus output voltage, standby mode (HVDA540, HVDA541 only) STB / S at VIO, RL = 60 Ω,
See Figure 2 and Figure 15 		–0.1 0.1 V
VOD(D) Differential output voltage (dominant) VI = 0 V, RL = 60 Ω, STB / S at 0 V,
See Figure 2, Figure 15, and Figure 3 		1.5 3 V
VI = 0 V, RL = 45 Ω, STB / S at 0 V,
See Figure 2, Figure 15, and Figure 3 		1.4 3
VOD(R) Differential output voltage (recessive) VI = 3 V, STB / S at 0 V, RL = 60 Ω, See Figure 2 and Figure 15 –0.012 0.012 V
VI = 3 V, STB / S at 0 V, No load –0.5 0.05
VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) STB / S at 0 V, RL = 60 Ω,
See Figure 12 		0.9 VCC VCC 1.1 VCC V
VOC(SS) Steady-state common-mode output voltage STB / S at 0 V, RL = 60 Ω,
See Figure 8 		2 2.5 3 V
ΔVOC(SS) Change in steady-state common-mode output voltage STB / S at 0 V, RL = 60 Ω,
See Figure 8 		40 mV
IOS(SS)_DOM Short-circuit steady-state output current, Dominant VCANH = 0 V, CANL open, TXD = low,
See Figure 11 		–100 mA
VCANL = 32 V, CANH open, TXD = low, See Figure 11 100
IOS(SS)_REC Short-circuit steady-state output current, Recessive –20 V ≤ VCANH ≤ 32 V, CANL open,
TXD = high, See Figure 11 		–10 10 mA
–20 V ≤ VCANL ≤ 32 V, CANH open,
TXD = high, See Figure 11 		–10 10
CO Output capacitance See receiver input capacitance
DRIVER SWITCHING CHARACTERISTICS
tPLH Propagation delay time, low-to-high level output STB / S at 0 V, See Figure 4 65 ns
tPHL Propagation delay time, high-to-low level output STB / S at 0 V, See Figure 4 50 ns
tR Differential output signal rise time STB / S at 0 V, See Figure 4 25 ns
tF Differential output signal fall time STB / S at 0 V, See Figure 4 55 ns
tEN Enable time from standby or silent mode to normal mode dominant See Figure 7 20 µs
t(DOM)(5) Dominant time out See Figure 10 300 400 700 µs
RECEIVER ELECTRICAL CHARACTERISTICS
VIT+ Positive-going input threshold voltage, normal mode STB / S at 0 V, See Table 1 800 900 mV
VIT– Negative-going input threshold voltage, normal mode STB / S at 0 V, See Table 1 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100 125 mV
VIT(STBY) Input threshold voltage, standby mode (HVDA541 only) STB at VIO 400 1150 mV
II(OFF_LKG) Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, VCC at 0 V,
VIO at 0 V, TXD at 0 V		 3 µA
CI Input capacitance to ground (CANH or CANL) HVDA54x: TXD at VIO, VIO at 3.3 V.
HVDA54x-5: TXD at VCC
VI = 0.4 sin (4E6πt) + 2.5 V		 13 pF
CID Differential input capacitance HVDA54x: TXD at VIO, VIO at 3.3 V.
HVDA54x-5: TXD at VCC
VI = 0.4 sin(4E6πt)		 5 pF
RID Differential input resistance HVDA54x: TXD at VIO, VIO = 3.3 V, STB at 0 V
HVDA54x-5: TXD at VCC, STB at 0 V		 29 80 kΩ
RIN Input resistance (CANH or CANL) 14.5 25 40 kΩ
RI(M) Input resistance matching
[1 – ®IN(CANH)/RIN(CANL))] × 100%		 V(CANH) = V(CANL) –3 0 3 %
RECEIVER SWITCHING CHARACTERISTICS
tPLH Propagation delay time, low-to-high-level output STB / S at 0 V , See Figure 6 95 ns
tPHL Propagation delay time, high-to-low-level output STB / S at 0 V , See Figure 6 60 ns
tR Output signal rise time STB / S at 0 V , See Figure 6 13 ns
tF Output signal fall time STB / S at 0 V , See Figure 6 10 ns
tBUS Dominant time required on bus for wake-up from standby (HVDA541 only) STB at VIO, See Figure 17 and Figure 18 1.5 5 µs
tCLEAR Recessive time on the bus to clear the standby mode receiver output (RXD) if standby mode is entered while bus is dominant (HVDA541 only) 1.5 5 µs
TXD PIN CHARACTERISTICS
VIH High-level input voltage HVD54x-5: VIO = VCC 0.7 × VIO V
VIL Low-level input voltage HVD54x-5: VIO = VCC 0.3 × VIO V
IIH High-level input current HVDA54x: TXD at VIO HVDA54x-5: TXD at VCC –2 2 µA
IIL Low-level input current TXD at 0 V –100 –7 µA
RXD PIN CHARACTERISTICS
VOH High-level output voltage IO = –2 mA, See Figure 6 HVD54x-5:
VIO = VCC		 0.8 × VIO V
VOL Low-level output voltage IO = 2 mA, See Figure 6 HVD54x-5:
VIO = VCC		 0.2 × VIO V
STB PIN CHARACTERISTICS (HVDA540 AND HVDA541 ONLY)
VIH High-level input voltage HVD54x-5: VIO = VCC 0.7 × VIO V
VIL Low-level input voltage HVD54x-5: VIO = VCC 0.3 × VIO V
IIH High-level input current HVDA54x: STB at VIO HVDA54x-5: STB at VCC –2 2 µA
IIL Low-level input current STB at 0 V –20 µA
S PIN CHARACTERISTICS (HVDA542 ONLY)
VIH High-level input voltage HVD54x-5: VIO = VCC 0.7 × VIO V
VIL Low-level input voltage HVD54x-5: VIO = VCC 0.3 × VIO V
IIH High-level input current HVDA54x: S at VIO HVDA54x-5: S at VCC 30 µA
IIL Low-level input current S at 0 V –2 2 µA
Thermal shutdown temperature 185 °C
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V.
(2) The VCC supply is not needed during standby mode so in the application ICC in standby mode may be zero. If the VCC supply remains, then ICC is per specification with VCC.
(4) For the HVDA542 device the bus output voltage (recessive) will be the same if the device is in normal mode with S pin at 0 V or if the device is in silent mode with the S pin at HIGH.
(5) The TXD dominant time out (t(DOM)) disables the driver of the transceiver once the TXD has been dominant longer than t(DOM), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t(DOM) = 11 bits / 300 µs = 37 kbps

6.6 Power Dissipation Ratings

over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices VIO = VCC
MIN TYP MAX UNIT
PD Average power dissipation VCC = 5 V, VIO = VCC, TJ = 27°C, RL = 60 Ω,
STB at 0 V, Input to TXD at 500 kHz,
50% duty cycle square wave,
CL at RXD = 15 pF		 140 mW
VCC = 5.33 V, VIO = VCC, TJ = 130°C,
RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF		 215

6.7 Typical Characteristics

SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA542-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 C001_SLLS804.png
STB = 0 V RL= 60 Ω CL= Open Rcm= open Temp = 25°C
Figure 1. HVDA540 VCC vs VOD from 4.5 V to 5.5 V