ZHCSB64A June 2013 – September 2014 SN6501-Q1
The SN6501-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two output transistors on and off.
The output frequency of the oscillator is divided down by an asynchronous divider that provides two complementary output signals with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time between the high-pulses of the two signals. The resulting output signals, present the gate-drive signals for the output transistors. As shown in the functional block diagram, before either one of the gates can assume logic high, there must be a short time period during which both signals are low and both transistors are high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of the primary.
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary (see Figure 37).
When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative voltage potential at the lower primary end with regards to the VIN potential at the center-tap.
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive with regards to the center-tap in order to maintain the previously established current flow through Q2, which now has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a voltage potential at the open end of the primary of 2×VIN with regards to ground.
Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load impedance RL back to the center-tap.
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse. Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2 is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2, charging the capacitor and returning through the load to the center-tap.
Figure 38 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2 conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON.
This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle. If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the transformer slowly creeps toward the saturation region.
Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of the SN6501 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is the difference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS, VP is gradually reduced and V-t balance restored.
The functional modes of the SN6501 are divided into start-up, operating, and off-mode.
When the supply voltage at Vcc ramps up to 2.4V typical, the internal oscillator starts operating at a start frequency of 300 kHz. The output stage begins switching but the amplitude of the drain signals at D1 and D2 has not reached its full maximum yet.
When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations over supply voltage and operating temperature can vary the switching frequencies at D1 and D2 between 250 kHz and 495 kHz for VCC = 3.3 V ±10%, and between 300 kHz and 620 kHz for VCC = 5 V ±10%.
The SN6501 is deactivated by reducing VCC to 0 V. In this state both drain outputs, D1 and D2, are high-impedance.