ZHCSNJ0G September   2006  – March 2021 PCA9538

PRODUCTION DATA  

  1. 1 特性
  2. 2 说明
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 RESET Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
      1. 7.2.1 RESET Input
        1. 7.2.1.1 RESET Errata
          1.        System Impact
          2.        System Workaround
      2. 7.2.2 Power-On Reset
      3. 7.2.3 I/O Port
      4. 7.2.4 Interrupt Output ( INT)
        1. 7.2.4.1 Interrupt Errata
          1.        System Impact
          2.        System Workaround
    3. 7.3 Programming
      1. 7.3.1 I2C Interface
    4. 7.4 Register Maps
      1. 7.4.1 Device Address
      2. 7.4.2 Control Register And Command Byte
      3. 7.4.3 Register Descriptions
      4. 7.4.4 Bus Transactions
        1. 7.4.4.1 Writes
        2. 7.4.4.2 Reads
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information Disclaimer
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Minimizing ICC When I/Os Control Leds
  9. 9 Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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7.4.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register is accessed next. See Table 7-4.

Table 7-4 Register 0 (Input Port Register) Table
BITI7I6I5I4I3I2I1I0
DEFAULTXXXXXXXX

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See Table 7-5.

Table 7-5 Register 1 (Output Port Register) Table
BITO7O6O5O4O3O2O1O0
DEFAULT11111111

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 7-6.

Table 7-6 Register 2 (Polarity Inversion Register) Table
BITN7N6N5N4N3N2N1N0
DEFAULT00000000

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. See Table 7-7.

Table 7-7 Register 3 (Configuration Register) Table
BITC7C6C5C4C3C2C1C0
DEFAULT11111111