ZHCSMO3D June   2020  – July 2021 OPA2863 , OPA4863 , OPA863

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: OPA863
    5. 7.5  Thermal Information: OPA2863
    6. 7.6  热性能信息:OPA4863
    7. 7.7  Electrical Characteristics: 10 V
    8. 7.8  Electrical Characteristics: 3 V
    9. 7.9  Typical Characteristics: VS = 10 V
    10. 7.10 Typical Characteristics: VS = 3 V
    11. 7.11 Typical Characteristics: VS = 3 V to 10 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
        1. 8.3.2.1 Overload Power Limit
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 Split-Supply Operation (±1.35 V to ±6.3 V)
      3. 8.4.3 Single-Supply Operation (2.7 V to 12.6 V)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Amplifier Gain Configurations
    2. 9.2 Low-Side Current Sensing
      1. 9.2.1 Design Requirements
    3. 9.3 Transimpedance Amplifier
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
    4. 9.4 Low-Power SAR ADC Driver and Reference Buffer
    5. 9.5 Front-End Gain and Filtering
    6. 9.6 Clamp-On Ultrasonic Flow Meter
    7. 9.7 Variable Reference Generator Using MDAC
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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Input Stage

The OPAx863 devices include a rail-to-rail input stage. The main stage differential pair using PNP bipolar transistors operates for common-mode input voltages from VS–– 0.2 V till VS+ – 1.6 V. The amplifier inputs transition into the auxiliary stage using NPN transistors for common-mode input voltages from VS+ – 1.6 V till VS+ + 0.2 V. The PNP and NPN input stages offer a gain-bandwidth product of 50 MHz and a voltage noise density of 5.9 nV/√ Hz. The offset voltage for the two input stages is matched to lie within the device specifications. The NPN input stage does not use the slew boost circuit during large-signal transient response. The input bias current for the PNP and NPN input stages is opposite in polarity, which adds an additional offset based on the values of the gain-setting and feedback resistors. A common-mode input voltage transition between these input stages will cause a crossover distortion which needs to be considered in high-frequency applications requiring superior linearity. Limit the common-mode input voltage to VS+ – 1.6 V (maximum) for main-stage operation across process and ambient temperature.

Since the OPAx863 devices are bipolar amplifiers, the two inputs are protected with anti-parallel back-to-back diodes between them, which limits the maximum input differential voltage to 1 V. The amplifier is slew limited, and the two inputs are pulled apart up to 1 V when the anti-parallel diodes begin to conduct in very fast input or output transient conditions. Care must be taken to use gain-setting and feedback resistors large enough to limit the current through these diodes in such conditions.