ZHCSDO6B May   2015  – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 8.7 Thermal Resistance Characteristics
    8. 8.8 Timing and Switching Characteristics
      1. 8.8.1  Power Supply Sequencing
        1. 8.8.1.1 Brownout and Device Reset Power Ramp Requirements
      2. 8.8.2  Reset Timing
        1. 8.8.2.1 Reset Input
      3. 8.8.3  Clock Specifications
        1. 8.8.3.1 Crystal Oscillator, XT1, Low-Frequency Mode
        2. 8.8.3.2 Crystal Oscillator, XT2
        3. 8.8.3.3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        4. 8.8.3.4 Internal Reference, Low-Frequency Oscillator (REFO)
        5. 8.8.3.5 DCO Frequency
      4. 8.8.4  Wake-up Characteristics
        1. 8.8.4.1 Wake-up Times From Low-Power Modes and Reset
      5. 8.8.5  General-Purpose I/Os
        1. 8.8.5.1 Schmitt-Trigger Inputs – General-Purpose I/O
        2. 8.8.5.2 Inputs – Ports P1, P2, P3, and P4
        3. 8.8.5.3 Leakage Current – General-Purpose I/O
        4. 8.8.5.4 Outputs – General-Purpose I/O (Full Drive Strength)
        5. 8.8.5.5 Outputs – General-Purpose I/O (Reduced Drive Strength)
        6. 8.8.5.6 Output Frequency – Ports P1, P2 and P3
        7. 8.8.5.7 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
        8. 8.8.5.8 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
      6. 8.8.6  PMM
        1. 8.8.6.1 PMM, Core Voltage
        2. 8.8.6.2 PMM, SVS High Side
        3. 8.8.6.3 PMM, SVM High Side
        4. 8.8.6.4 PMM, SVS Low Side
        5. 8.8.6.5 PMM, SVM Low Side
      7. 8.8.7  Timers
        1. 8.8.7.1 Timer_A, Timers TA0, TA1, and TA2
        2. 8.8.7.2 Timer_B, Timer TB0
      8. 8.8.8  Battery Backup
        1. 8.8.8.1 Battery Backup
      9. 8.8.9  USCI
        1. 8.8.9.1 USCI (UART Mode)
        2. 8.8.9.2 USCI (SPI Master Mode)
        3. 8.8.9.3 USCI (SPI Slave Mode)
        4. 8.8.9.4 USCI (I2C Mode)
      10. 8.8.10 LCD Controller
        1. 8.8.10.1 LCD_B Operating Conditions
        2. 8.8.10.2 LCD_B, Electrical Characteristics
      11. 8.8.11 CTSD16
        1. 8.8.11.1 CTSD16, Power Supply and Operating Conditions
        2.       66
        3. 8.8.11.2 CTSD16, External Voltage Reference
        4. 8.8.11.3 CTSD16, Input Range
        5. 8.8.11.4 CTSD16, Performance
        6.       70
        7. 8.8.11.5 Built-in Vcc Sense
        8. 8.8.11.6 Temperature Sensor
      12. 8.8.12 REF
        1. 8.8.12.1 REF and REFBG, Built-In Reference
      13. 8.8.13 DAC
        1. 8.8.13.1 12-Bit DAC, Supply Specifications
        2. 8.8.13.2 12-Bit DAC, Linearity Specifications
        3. 8.8.13.3 12-Bit DAC, Output Specifications
        4. 8.8.13.4 12-Bit DAC, Reference Input Specifications
        5. 8.8.13.5 12-Bit DAC, Dynamic Specifications
        6. 8.8.13.6 12-Bit DAC, Dynamic Specifications (Continued)
      14. 8.8.14 Operational Amplifier
        1. 8.8.14.1 Operational Amplifier, OA0, OA1, PGA Buffers
        2. 8.8.14.2 OA, Current Calculation
      15. 8.8.15 Switches
        1. 8.8.15.1 Ground Switches (GSW0A, GSW0B, GSW1A, GSW1B)
        2. 8.8.15.2 Operational Amplifier Switches
      16. 8.8.16 Comparator
        1. 8.8.16.1 Comparator_B
      17. 8.8.17 USB
        1. 8.8.17.1 Ports PU.0 and PU.1
        2. 8.8.17.2 USB Output Ports DP and DM
        3. 8.8.17.3 USB Input Ports DP and DM
        4. 8.8.17.4 USB-PWR (USB Power System)
        5. 8.8.17.5 USB-PLL (USB Phase-Locked Loop)
      18. 8.8.18 LDO-PWR (LDO Power System)
        1. 8.8.18.1 LDO-PWR (LDO Power System)
      19. 8.8.19 Flash
        1. 8.8.19.1 Flash Memory
      20. 8.8.20 Debug and Emulation
        1. 8.8.20.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  USB BSL
    7. 9.7  UART BSL
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY32)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 Signal Chain
        1. 9.12.16.1 CTSD16
        2. 9.12.16.2 DAC12_A
        3. 9.12.16.3 Operational Amplifiers (OA)
        4. 9.12.16.4 Ground Switches (GSW)
      17. 9.12.17 REF Voltage Reference
      18. 9.12.18 CRC16
      19. 9.12.19 LCD_B
      20. 9.12.20 USB Universal Serial Bus
      21. 9.12.21 LDO and PU Port
      22. 9.12.22 Embedded Emulation Module (EEM) (L Version)
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.1 and P5.6) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P5 (P5.3 to P5.5, P5.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P6 (P6.0 to P6.1) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P6 (P6.2 and P6.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P6 (P6.4) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P6 (P6.5) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P6 (P6.6) Input/Output With Schmitt Trigger
      13. 9.13.13 Port P6 (P6.7) Input/Output With Schmitt Trigger
      14. 9.13.14 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
      15. 9.13.15 Port P7 (P7.4) Input/Output With Schmitt Trigger
      16. 9.13.16 Port P7 (P7.5) Input/Output With Schmitt Trigger
      17. 9.13.17 Port P7 (P7.6) Input/Output With Schmitt Trigger
      18. 9.13.18 Port P7 (P7.7) Input/Output With Schmitt Trigger
      19. 9.13.19 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      20. 9.13.20 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      21. 9.13.21 Port U (PU.0/DP, PU.1/DM, PUR) USB Ports for MSP430FG662x
      22. 9.13.22 Port J (J.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      23. 9.13.23 Port J (J.1 to J.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
    15. 9.15 Memory
      1. 9.15.1 Peripheral File Map
    16. 9.16 Identification
      1. 9.16.1 Revision Identification
      2. 9.16.2 Device Identification
      3. 9.16.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 CTSD16 Peripheral
        1. 10.2.1.1 Example Measurement Schematic – Differential Input
        2. 10.2.1.2 Example Measurement Schematic – Single-Ended Input
        3. 10.2.1.3 Design Requirements
        4. 10.2.1.4 Detailed Design Procedure
          1. 10.2.1.4.1 OSR and Sampling Frequency
          2. 10.2.1.4.2 Differential Input Range Explanation
          3. 10.2.1.4.3 Single-Ended Input Mode
          4. 10.2.1.4.4 Offset Calibration
        5. 10.2.1.5 Layout Guidelines
      2. 10.2.2 Operational Amplifier With Ground Switches Peripheral
        1. 10.2.2.1 Reference Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
      3. 10.2.3 RTC_B With Battery Backup System
        1. 10.2.3.1 Partial Schematic
        2. 10.2.3.2 Retaining an Accurate Real-Time Clock (RTC) Through Main Supply Interrupts
        3. 10.2.3.3 Charging Super-Capacitors With Built-In Resistive Charger
      4. 10.2.4 LCD_B Peripheral
        1. 10.2.4.1 Partial Schematic
        2. 10.2.4.2 Design Requirements
        3. 10.2.4.3 Detailed Design Procedure
        4. 10.2.4.4 Layout Guidelines
      5. 10.2.5 DAC12 Peripheral
        1. 10.2.5.1 Partial Schematic
        2. 10.2.5.2 Design Requirements
        3. 10.2.5.3 Detailed Design Procedure
        4. 10.2.5.4 Layout Guidelines
      6. 10.2.6 USB Module
      7. 10.2.7 LDO Module
        1. 10.2.7.1 Partial Schematic
  11. 11Device and Documentation Support
    1. 11.1  Getting Started
    2. 11.2  Device Nomenclature
    3. 11.3  Tools and Software
    4. 11.4  Documentation Support
    5. 11.5  Related Links
    6. 11.6  支持资源
    7. 11.7  Trademarks
    8. 11.8  静电放电警告
    9. 11.9  Export Control Notice
    10. 11.10 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

封装选项

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订购信息

7.2 Pin Attributes

Table 7-1 describes the attributes of the pins.

Table 7-1 Pin Attributes
PIN NO. SIGNAL NAME (1) (2) SIGNAL TYPE (3) BUFFER TYPE (4) POWER SOURCE(5) RESET STATE AFTER BOR (6)(7)
PZ ZCA, ZQW
1 A1 P6.4 I/O LVCMOS DVCC OFF
CB4 I Analog DVCC N/A
AD0+ I Analog DVCC N/A
OA0O O Analog DVCC N/A
2 B2 P6.5 I/O LVCMOS DVCC OFF
CB5 I Analog DVCC N/A
AD0- I Analog DVCC N/A
OA0IN0 I Analog DVCC N/A
3 B1 P6.6 I/O LVCMOS DVCC OFF
CB6 I Analog DVCC N/A
AD1+ I Analog DVCC N/A
G0SW0 I Analog DVCC N/A
4 C3 P6.7 I/O LVCMOS DVCC OFF
CB7 I Analog DVCC N/A
AD1- I Analog DVCC N/A
G0SW1 I Analog DVCC N/A
5 C2 P7.4 I/O LVCMOS DVCC OFF
CB8 I Analog DVCC N/A
AD2+ I Analog DVCC N/A
OA1O O Analog DVCC N/A
6 C1 P7.5 I/O LVCMOS DVCC OFF
CB9 I Analog DVCC N/A
AD2- I Analog DVCC N/A
OA1IN0 I Analog DVCC N/A
7 D4 P7.6 I/O LVCMOS DVCC OFF
CB10 I Analog DVCC N/A
AD3+ I Analog DVCC N/A
G1SW0 I Analog DVCC N/A
8 D2 P7.7 I/O LVCMOS DVCC OFF
CB11 I Analog DVCC N/A
AD3- I Analog DVCC N/A
G1SW1 I Analog DVCC N/A
9 D1 P5.0 I/O LVCMOS DVCC OFF
VREFBG O Analog DVCC N/A
VeREF+ I Analog N/A N/A
10 E4 P5.1 I/O LVCMOS DVCC OFF
A4 I Analog DVCC N/A
DAC0 O Analog DVCC N/A
11 E2 P5.6 I/O LVCMOS DVCC OFF
A5 I Analog DVCC N/A
DAC1 O Analog DVCC N/A
12 E1 NR I Analog N/A N/A
13 F2 AVSS1 P Power N/A N/A
14 F1 XOUT O Analog N/A N/A
15 G1 XIN I Analog N/A N/A
16 H1, G2 AVCC P Power N/A N/A
17 G4 CPCAP I/O Analog DVCC N/A
18 H2 P2.0 I/O LVCMOS DVCC OFF
P2MAP0 I/O LVCMOS DVCC N/A
DAC0 O Analog DVCC N/A
19 J1 P2.1 I/O LVCMOS DVCC OFF
P2MAP1 I/O LVCMOS DVCC N/A
DAC1 O Analog DVCC N/A
20 H4 P2.2 I/O LVCMOS DVCC OFF
P2MAP2 I/O LVCMOS DVCC N/A
21 J2 P2.3 I/O LVCMOS DVCC OFF
P2MAP3 I/O LVCMOS DVCC N/A
22 K1 P2.4 I/O LVCMOS DVCC OFF
P2MAP4 I/O LVCMOS DVCC N/A
R03 I/O Analog DVCC N/A
23 K2 P2.5 I/O LVCMOS DVCC OFF
P2MAP5 I/O LVCMOS DVCC N/A
24 L2 P2.6 I/O LVCMOS DVCC OFF
P2MAP6 I/O LVCMOS DVCC N/A
LCDREF I Analog N/A N/A
R13 I/O Analog DVCC N/A
25 L3 P2.7 I/O LVCMOS DVCC OFF
P2MAP7 I/O LVCMOS DVCC N/A
R23 I/O Analog DVCC N/A
26 L1 DVCC1 P Power N/A N/A
27 M1 DVSS1 P Power N/A N/A
28 M2 VCORE P Power DVCC N/A
29 M3 LCDCAP I/O Analog DVCC N/A
R33 I/O Analog DVCC N/A
30 J4 COM0 O Analog DVCC N/A
31 L4 P5.3 I/O LVCMOS DVCC OFF
COM1 O Analog DVCC N/A
S42 O Analog DVCC N/A
32 M4 P5.4 I/O LVCMOS DVCC OFF
COM2 O LVCMOS DVCC N/A
S41 O Analog DVCC N/A
33 J5 P5.5 I/O LVCMOS DVCC OFF
COM3 I/O LVCMOS DVCC N/A
S40 O Analog DVCC N/A
34 L5 P1.0 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC N/A
ACLK O LVCMOS DVCC N/A
S39 O Analog DVCC N/A
35 M5 P1.1 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC N/A
BSLTX O LVCMOS DVCC N/A
S38 O Analog DVCC N/A
36 J6 P1.2 I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC N/A
BSLRX I LVCMOS DVCC N/A
S37 O Analog DVCC N/A
37 H6 P1.3 I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC N/A
S36 O Analog DVCC N/A
38 M6 P1.4 I/O LVCMOS DVCC OFF
TA0.3 I/O LVCMOS DVCC N/A
S35 O Analog DVCC N/A
39 L6 P1.5 I/O LVCMOS DVCC OFF
TA0.4 I/O LVCMOS DVCC N/A
S34 O Analog DVCC N/A
40 J7 P1.6 I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC N/A
S33 O Analog DVCC N/A
41 M7 P1.7 I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC N/A
S32 O Analog DVCC N/A
42 L7 P3.0 I/O LVCMOS DVCC OFF
TA1CLK I LVCMOS DVCC N/A
CBOUT O LVCMOS DVCC N/A
S31 O Analog DVCC N/A
43 H7 P3.1 I/O LVCMOS DVCC OFF
TA1.0 I/O LVCMOS DVCC N/A
S30 O Analog DVCC N/A
44 M8 P3.2 I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC N/A
S29 O Analog DVCC N/A
45 L8 P3.3 I/O LVCMOS DVCC OFF
TA1.2 I/O LVCMOS DVCC N/A
S28 O Analog DVCC N/A
46 J8 P3.4 I/O LVCMOS DVCC OFF
TA2CLK I LVCMOS DVCC N/A
SMCLK O LVCMOS DVCC N/A
S27 O Analog DVCC N/A
47 M9 P3.5 I/O LVCMOS DVCC OFF
TA2.0 I/O LVCMOS DVCC N/A
S26 O Analog DVCC N/A
48 L9 P3.6 I/O LVCMOS DVCC OFF
TA2.1 I/O LVCMOS DVCC N/A
S25 O Analog DVCC N/A
49 M10 P3.7 I/O LVCMOS DVCC OFF
TA2.2 I/O LVCMOS DVCC N/A
S24 O Analog DVCC N/A
50 J9 P4.0 I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC N/A
S23 O Analog DVCC N/A
51 M11 P4.1 I/O LVCMOS DVCC OFF
TB0.1 I/O LVCMOS DVCC N/A
S22 O Analog DVCC N/A
52 L10 P4.2 I/O LVCMOS DVCC OFF
TB0.2 I/O LVCMOS DVCC N/A
S21 O Analog DVCC N/A
53 M12 P4.3 I/O LVCMOS DVCC OFF
TB0.3 I/O LVCMOS DVCC N/A
S20 O Analog DVCC N/A
54 L12 P4.4 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC N/A
S19 O Analog DVCC N/A
55 L11 P4.5 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC N/A
S18 O Analog DVCC N/A
56 K11 P4.6 I/O LVCMOS DVCC OFF
TB0.6 I/O LVCMOS DVCC N/A
S17 O Analog DVCC N/A
57 K12 P4.7 I/O LVCMOS DVCC OFF
TB0OUTH I LVCMOS DVCC N/A
SVMOUT O LVCMOS DVCC N/A
S16 O Analog DVCC N/A
58 J11 P8.0 I/O LVCMOS DVCC OFF
TB0CLK I LVCMOS DVCC N/A
S15 O Analog DVCC N/A
59 J12 P8.1 I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC N/A
UCA1CLK I/O LVCMOS DVCC N/A
S14 O Analog DVCC N/A
60 H11 P8.2 I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC N/A
UCA1SIMO I/O LVCMOS DVCC N/A
S13 O Analog DVCC N/A
61 H12 P8.3 I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC N/A
UCA1SOMI I/O LVCMOS DVCC N/A
S12 O Analog DVCC N/A
62 G11 P8.4 I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC N/A
UCA1STE I/O LVCMOS DVCC N/A
S11 O Analog DVCC N/A
63 G12 DVSS2 P Power N/A N/A
64 F12 DVCC2 P Power N/A N/A
65 F11 P8.5 I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC N/A
UCB1SDA I/O LVCMOS DVCC N/A
S10 O Analog DVCC N/A
66 G9 P8.6 I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC N/A
UCB1SCL I/O LVCMOS DVCC N/A
S9 O Analog DVCC N/A
67 E12 P8.7 I/O LVCMOS DVCC OFF
S8 O Analog DVCC N/A
68 E11 P9.0 I/O LVCMOS DVCC OFF
S7 O Analog DVCC N/A
69 F9 P9.1 I/O LVCMOS DVCC OFF
S6 O Analog DVCC N/A
70 D12 P9.2 I/O LVCMOS DVCC OFF
S5 O Analog DVCC N/A
71 D11 P9.3 I/O LVCMOS DVCC OFF
S4 O Analog DVCC N/A
72 E9 P9.4 I/O LVCMOS DVCC OFF
S3 O Analog DVCC N/A
73 C12 P9.5 I/O LVCMOS DVCC OFF
S2 O Analog DVCC N/A
74 C11 P9.6 I/O LVCMOS DVCC OFF
S1 O Analog DVCC N/A
75 D9 P9.7 I/O LVCMOS DVCC OFF
S0 O Analog DVCC N/A
76 B11, B12 VSSU P Power N/A N/A
77 A12 PU.0 I/O HVCMOS VBUS HiZ
DP I/O HVCMOS VBUS N/A
78 B10 PUR (FG662x only) I/O HVCMOS/open-drain VBUS HiZ
NC (FG642x only) I/O N/A N/A N/A
79 A11 PU.1 I/O HVCMOS VBUS HiZ
DM I/O HVCMOS VBUS N/A
80 A10 VBUS I Power N/A N/A
LDOI I Analog External N/A
81 A9 VUSB O Power N/A N/A
LDOO O Analog VBUS N/A
82 B9 V18 (FG662x only) O Power N/A N/A
NC (FG642x only) – N/A N/A N/A
83 A8 AVSS2 P Power N/A N/A
84 B8 P7.2 I/O LVCMOS DVCC OFF
XT2IN I Analog DVCC N/A
85 B7 P7.3 I/O LVCMOS DVCC OFF
XT2OUT O Analog DVCC N/A
86 A7 VBAK I/O Analog N/A N/A
87 D8 VBAT P Power N/A N/A
88 D7 P5.7 I/O LVCMOS DVCC OFF
DMAE0 I LVCMOS DVCC N/A
RTCCLK O LVCMOS DVCC N/A
89 A6 DVCC3 P Power N/A N/A
90 A5 DVSS3 P Power N/A N/A
91 B6 TEST I LVCMOS DVCC No Emu: PD
Emu: PD
SBWTCK I LVCMOS DVCC N/A
92 B5 PJ.0 I/O LVCMOS DVCC OFF
TDO O LVCMOS DVCC No Emu: OFF
Emu: DRIVE0
93 A4 PJ.1 I/O LVCMOS DVCC OFF
TDI I LVCMOS DVCC No Emu: OFF
Emu: PU
TCLK I LVCMOS DVCC No Emu: OFF
Emu: OFF
94 E7 PJ.2 I/O LVCMOS DVCC OFF
TMS I LVCMOS DVCC No Emu: OFF
Emu: PU
95 D6 PJ.3 I/O LVCMOS DVCC OFF
TCK I LVCMOS DVCC No Emu: OFF
Emu: PU
96 A3 RST I/O LVCMOS DVCC PU
NMI I LVCMOS DVCC N/A
SBWTDIO I/O LVCMOS DVCC PU
97 B4 P6.0 I/O LVCMOS DVCC OFF
CB0 I Analog DVCC N/A
A0 I Analog DVCC N/A
98 B3 P6.1 I/O LVCMOS DVCC OFF
CB1 I Analog DVCC N/A
A1 I Analog DVCC N/A
99 A2 P6.2 I/O LVCMOS DVCC OFF
CB2 I Analog DVCC N/A
A2 I Analog DVCC N/A
OA0IP0 I Analog DVCC N/A
100 D5 P6.3 I/O LVCMOS DVCC OFF
CB3 I Analog DVCC N/A
A3 I Analog DVCC N/A
OA1IP0 I Analog DVCC N/A
N/A E5, E6, E8, F4, F5, F8, G5, G8, H5, H8, H9 Reserved - – – –
(1) For each multiplexed pin, the signal that is listed first in this table is the reset default.
(2) To determine the pin mux encodings for each pin, refer to Section 9.13.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
(4) Buffer Types: LVCMOS, HVCMOS, Analog, or Power (see Table 7-3 for details).
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
HiZ = High-impedance (neither input nor output)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable
(7) For Debug pins: Emu = with emulator attached at reset, No Emu = without emulator attached at reset