ZHCSQG6A March   2022  – May 2022 LP5891

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Independent and Stackable Mode
        1. 7.3.1.1 Independent Mode
        2. 7.3.1.2 Stackable Mode
      2. 7.3.2 Current Setting
        1. 7.3.2.1 Brightness Control (BC) Function
        2. 7.3.2.2 Color Brightness Control (CC) Function
        3. 7.3.2.3 Choosing BC/CC for a Different Application
      3. 7.3.3 Frequency Multiplier
      4. 7.3.4 Line Transitioning Sequence
      5. 7.3.5 Protections and Diagnostics
        1. 7.3.5.1 Thermal Shutdown Protection
        2. 7.3.5.2 IREF Resistor Short Protection
        3. 7.3.5.3 LED Open Load Detection and Removal
          1. 7.3.5.3.1 LED Open Detection
          2. 7.3.5.3.2 Read LED Open Information
          3. 7.3.5.3.3 LED Open Caterpillar Removal
        4. 7.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 7.3.5.4.1 LED Short/Weak Short Detection
          2. 7.3.5.4.2 Read LED Short Information
          3. 7.3.5.4.3 LSD Caterpillar Removal
    4. 7.4 Device Functional Modes
    5. 7.5 Continuous Clock Series Interface
      1. 7.5.1 Data Validity
      2. 7.5.2 CCSI Frame Format
      3. 7.5.3 Write Command
        1. 7.5.3.1 Chip Index Write Command
        2. 7.5.3.2 VSYNC Write Command
        3. 7.5.3.3 MPSM Write Command
        4. 7.5.3.4 Standby Clear and Enable Command
        5. 7.5.3.5 Soft_Reset Command
        6. 7.5.3.6 Data Write Command
      4. 7.5.4 Read Command
    6. 7.6 PWM Grayscale Control
      1. 7.6.1 Grayscale Data Storage and Display
        1. 7.6.1.1 Memory Structure Overview
        2. 7.6.1.2 Details of Memory Bank
        3. 7.6.1.3 Write a Frame Data into Memory Bank
      2. 7.6.2 PWM Control for Display
    7. 7.7 Register Maps
      1. 7.7.1  FC0
      2. 7.7.2  FC1
      3. 7.7.3  FC2
      4. 7.7.4  FC3
      5. 7.7.5  FC4
      6. 7.7.6  FC14
      7. 7.7.7  FC15
      8. 7.7.8  FC16
      9. 7.7.9  FC17
      10. 7.7.10 FC18
      11. 7.7.11 FC19
      12. 7.7.12 FC20
      13. 7.7.13 FC21
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 System Structure
        2. 8.2.1.2 SCLK Frequency
        3. 8.2.1.3 Internal GCLK Frequency
        4. 8.2.1.4 Line Switch Time
        5. 8.2.1.5 Blank Time Removal
        6. 8.2.1.6 BC and CC
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Chip Index Command
        2. 8.2.2.2 FC Registers Settings
        3. 8.2.2.3 Grayscale Data Write
        4. 8.2.2.4 VSYNC Command
        5. 8.2.2.5 LED Open/Short Read
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RRF|76
  • ZXL|96
散热焊盘机械数据 (封装 | 引脚)

7.6.2 PWM Control for Display

To increase the refresh rate in time-multiplexing display system, a DS-PWM (Dynamic Spectrum-Pulse Width Modulation) algorithm is proposed in this device. One frame is divided into many segments shown below. Note that one frame is divided into n sub-periods, n is set by SUBP_NUM (FC0 register bit24-22), and each sub-period is divided into 32 segments for 32 scan lines. Each segment contains GS GCLKs time for grayscale data display and T_SW GCLKs time for switching lines. GS is configured by the SEG_LENGTH (FC1 register bit9-0 in Table 7-8) , and T_SW is the line switch time, which is configured by the LINE_SWT (see FC1 register bit 40-37 in Table 7-8).

GUID-20220224-SS0I-LNLX-VZ0L-ZFBW0QDCRM7K-low.gif Figure 7-28 DS-PWM Algorithm with 32 Scan Lines

The DS-PWM can not only increase the refresh rate meanwhile keep the same frame rate, but also decrease the brightness loss in low grayscale, which can smoothly increase the sub-period number when the grayscale data increases.

To achieve ultra-low luminance, the LED driver must have the ability to output a very short current pulse (1 GCLK time), however, because of the parasitic capacitor of the LEDs, such pulse can not turn on the LEDs. The larger GCLK frequency is, the harder to turn on LEDs.

DS-PWM algorithm have a parameter called subperiod threshold, which is used to calculate when to change subperiod number according to the giving grayscale data. Subperiod threshold defines the LED minimum turn-on time, so as to conquer the current loss caused by LED parasitic capacitor. Subperiod threshold is configured by the LG_STEP_R/G/B (FC1 register bit24-10 in Table 7-8).

With DS-PWM algorithm, the brightness has smoothly increased with the gradient grayscale data.