ZHCSEK3 数据表 | 德州仪器 TI.com.cn

ZHCSEK3G December 2015 – August 2022 LMX2592

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

RHA|40

散热焊盘机械数据 (封装 | 引脚)

RHA|40
- QFND114P

订购信息

7.6.1 LMX2592 Register Map – Default Values

Figure 7-5 Register Table

REG	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REG	R/W	ADDRESS[6:0]							DATA [15:0]
0	R/W	0	0	0	0	0	0	0	0	0	LD_EN	0	0	0	1	FCAL_HPFD_ADJ		FCAL_LPFD_ADJ		ACAL_EN	FCAL_EN	MUXOUT_SEL	RESET	POWERDOWN
1	R/W	0	0	0	0	0	0	1	0	0	0	0	1	0	0	0	0	0	0	0	1	CAL_CLK_DIV
2	R/W	0	0	0	0	0	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0
4	R/W	0	0	0	0	1	0	0	ACAL_CMP_DLY								0	1	0	0	0	0	1	1
7	R/W	0	0	0	0	1	1	1	0	0	1	0	1	0	0	0	1	0	1	1	0	0	1	0
8	R/W	0	0	0	1	0	0	0	0	0	VCO_IDAC_OVR	1	0	VCO_CAPCTRL_OVR	0	0	1	0	0	0	0	1	0	0
9	R/W	0	0	0	1	0	0	1	0	0	0	0	OSC_2X	0	REF_EN	1	0	0	0	0	0	0	1	0
10	R/W	0	0	0	1	0	1	0	0	0	0	1	MULT					1	0	1	1	0	0	0
11	R/W	0	0	0	1	0	1	1	0	0	0	0	PLL_R								1	0	0	0
12	R/W	0	0	0	1	1	0	0	0	1	1	1	PLL_R_PRE
13	R/W	0	0	0	1	1	0	1	0	CP_EN	0	0	0	0	0	0	0	0	0	0	0	0	PFD_CTL
14	R/W	0	0	0	1	1	1	0	0	0	0	0	CP_IDN					CP_IUP					CP_ICOARSE
19	R/W	0	0	1	0	0	1	1	0	0	0	0	VCO_IDAC									1	0	1
20	R/W	0	0	1	0	1	0	0	0	0	0	0	0	0	0	ACAL_VCO_IDAC_STRT
22	R/W	0	0	1	0	1	1	0	0	0	1	0	0	0	1	1	VCO_CAPCTRL
23	R/W	0	0	1	0	1	1	1	1	FCAL_VCO_SEL_STRT	VCO_SEL			VCO_SEL_FORCE	0	0	0	1	0	0	0	0	1	0
24	R/W	0	0	1	1	0	0	0	0	0	0	0	0	1	0	1	0	0	0	0	1	0	0	1
25	R/W	0	0	1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
28	R/W	0	0	1	1	1	0	0	0	0	1	0	1	0	0	1	0	0	1	0	0	1	0	0
29	R/W	0	0	1	1	1	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0
30	R/W	0	0	1	1	1	1	0	0	0	0	0	0	MASH_DITHER	0	0	VTUNE_ADJ		1	1	0	1	0	VCO_2X_EN
31	R/W	0	0	1	1	1	1	1	0	0	0	0	0	VCO_DISTB_PD	VCO_DISTA_PD	0	CHDIV_DIST_PD	0	0	0	0	0	0	1
32	R/W	0	1	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	0	0	1	0	1	0
33	R/W	0	1	0	0	0	0	1	0	0	1	0	1	0	1	0	0	0	0	0	1	0	1	0
34	R/W	0	1	0	0	0	1	0	1	1	0	0	0	0	1	1	1	1	CHDIV_EN	0	1	0	1	0
35	R/W	0	1	0	0	0	1	1	0	0	0	CHDIV_SEG2				CHDIV_SEG3_EN	CHDIV_SEG2_EN	0	0	1	1	CHDIV_SEG1	CHDIV_SEG1_EN	1
36	R/W	0	1	0	0	1	0	0	0	0	0	0	CHDIV_DISTB_EN	CHDIV_DISTA_EN	0	0	0	CHDIV_SEG_SEL			CHDIV_SEG3
37	R/W	0	1	0	0	1	0	1	0	1	0	PLL_N_PRE	0	0	0	0	0	0	0	0	0	0	0	0
38	R/W	0	1	0	0	1	1	0	0	0	0	PLL_N												0
39	R/W	0	1	0	0	1	1	1	1	0	PFD_DLY						0	0	0	0	0	1	0	0
40	R/W	0	1	0	1	0	0	0	PLL_DEN[31:16]
41	R/W	0	1	0	1	0	0	1	PLL_DEN[15:0]
42	R/W	0	1	0	1	0	1	0	MASH_SEED[31:16]
43	R/W	0	1	0	1	0	1	1	MASH_SEED[15:0]
44	R/W	0	1	0	1	1	0	0	PLL_NUM[31:16]
45	R/W	0	1	0	1	1	0	1	PLL_NUM[15:0]
46	R/W	0	1	0	1	1	1	0	0	0	OUTA_POW						OUTB_PD	OUTA_PD	1	0	0	MASH_ORDER
47	R/W	0	1	0	1	1	1	1	0	0	0	OUTA_MUX		0	0	0	1	1	OUTB_POW
48	R/W	0	1	1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	OUTB_MUX
59	R/W	0	1	1	1	0	1	1	0	0	0	0	0	0	0	0	0	0	MUXOUT_HDRV	0	0	0	0	0
61	R/W	0	1	1	1	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	LD_TYPE
62	R/W	0	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
64	R/W	1	0	0	0	0	0	0	0	0	0	0	0	0	ACAL_FAST	FCAL_FAST	AJUMP_SIZE			1	FJUMP_SIZE
68	R	1	0	0	0	1	0	0	0	0	0	0	0	rb_LD_VTUNE		0	rb_VCO_SEL			0	0	0	0	0
69	R	1	0	0	0	1	0	1	0	0	0	0	0	0	0	0	rb_VCO_CAPCTRL
70	R	1	0	0	0	1	1	0	0	0	0	0	0	0	0	rb_VCO_DACISET