ZHCSPZ0A 数据表 | 德州仪器 TI.com.cn

ZHCSPZ0A february 2022 – june 2023 LMK1D1208I

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机械数据 (封装 | 引脚)

RHA|40
- MPQF135D

散热焊盘机械数据 (封装 | 引脚)

RHA|40
- QFND027R

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9.6.1 LMK1D1208I Registers

Table 9-10 lists the LMK1D1208I registers. All register locations not listed should be considered as reserved locations and the register contents should not be modified.

TI highly suggests that the user only operates within the logic states listed in Table 9-3 for optimum performance.

Table 9-10 LMK1D1208I Registers

Address	Acronym	Register Fields	Section
0h	R0	Output Enable Control	Go
1h	R1	Output Amplitude Control	Go
2h	R2	Input Enable and Bank Setting Control	Go
5h	R5	Device/Revision Identification	Go
Eh	R14	I²C Address Readback	Go

Complex bit access types are encoded to fit into small table cells. Table 9-11 shows the codes that are used for access types in this section.

Table 9-11 LMK1D1208I Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Reset/default value in hexadecimal

9.6.1.1 R0 Register (Address = 0h) [reset = 0h]

R0 is shown in Table 9-12.

The R0 register contains bits that enable or disable individual output clock channels [7:0].

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Table 9-12 R0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OUT7_EN	R/W	0h	This bit controls the output enable signal for output channel OUT7_P/OUT7_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled
6	OUT6_EN	R/W	0h	This bit controls the output enable signal for output channel OUT6_P/OUT6_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled
5	OUT5_EN	R/W	0h	This bit controls the output enable signal for output channel OUT5_P/OUT5_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled
4	OUT4_EN	R/W	0h	This bit controls the output enable signal for output channel OUT4_P/OUT4_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled
3	OUT3_EN	R/W	0h	This bit controls the output enable signal for output channel OUT3_P/OUT3_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled
2	OUT2_EN	R/W	0h	This bit controls the output enable signal for output channel OUT2_P/OUT2_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled
1	OUT1_EN	R/W	0h	This bit controls the output enable signal for output channel OUT1_P/OUT1_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled
0	OUT0_EN	R/W	0h	This bit controls the output enable signal for output channel OUT0_P/OUT0_N. 0h = Output Disabled (Hi-Z) 1h = Output Enabled

9.6.1.2 R1 Register (Address = 1h) [reset = 0h]

R1 is shown in Table 9-13.

The R1 register contains bits that set the output amplitude to a standard or boosted LVDS swing.

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Table 9-13 R1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OUT7_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT7_P/OUT7_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV)
6	OUT6_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT6_P/OUT6_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV)
5	OUT5_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT5_P/OUT5_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV)
4	OUT4_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT4_P/OUT4_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV)
3	OUT3_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT3_P/OUT3_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV)
2	OUT2_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT2_P/OUT2_N. 0h = Standard LVDS swing (350 mV) 1h = Boosted LVDS swing (500 mV)
1	OUT1_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT1_P/OUT1_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV)
0	OUT0_AMP_SEL	R/W	0h	This bit sets the output amplitude for output channel OUT0_P/OUT0_N. 0h = Standard LVDS Swing (350 mV) 1h = Boosted LVDS Swing (500 mV)

9.6.1.3 R2 Register (Address = 2h) [reset = F1h]

R2 is shown in Table 9-14.

The R2 register contains bits that enable/disable the input channels and control the banks.

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Table 9-14 R2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	1h	Register bit can be written to 1. Writing a different value than 1 will affect device functionality.
6	Reserved	R/W	1h	Register bit can be written to 1. Writing a different value than 1 will affect device functionality.
5	BANK1_IN_SEL	R/W	1h	This bit sets the input channel for Bank 1. 0h = IN1_P/IN1_N 1h = IN0_P/IN0_N
4	BANK0_IN_SEL	R/W	1h	This bit sets the input channel for Bank 0. 0h = IN1_P/IN1_N 1h = IN0_P/IN0_N
3	BANK1_MUTE	R/W	0h	This bit sets the outputs in Bank 1 to logic low level. 0h = INx_P/INx_N 1h = Logic low
2	BANK0_MUTE	R/W	0h	This bit sets the outputs in Bank 0 to logic low level. 0h = INx_P/INx_N 1h = Logic low
1	IN1_EN	R/W	0h	This bit controls the input enable signal for input channel IN1_P/IN1_N. 0h = Input Disabled (reduces power consumption) 1h = Input Enabled
0	IN0_EN	R/W	1h	This bit controls the input enable signal for input channel IN0_P/IN0_N. 0h = Input Disabled (reduces power consumption) 1h = Input Enabled

9.6.1.4 R5 Register (Address = 5h) [reset = 20h]

R5 is shown in Table 9-15.

The R5 register contains the silicon revision code and the device identification code.

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Table 9-15 R5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	REV_ID	R	2h	These bits provide the silicon revision code.
3:0	DEV_ID	R	0h	These bits provide the device identification code.

9.6.1.5 R14 Register (Address = Eh) [reset = 0h]

R14 is shown in Table 9-16.

The R14 register contains the bits that report the current state of the I²C address based on the IDX0 and IDX1 input pins.

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Table 9-16 R14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	IDX_RB	R	0h	These bits report the I²C address state.