ZHCSPZ0A february   2022  – june 2023 LMK1D1208I

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
      2. 9.3.2 Input Stage Configurability
      3. 9.3.3 Dual Output Bank
      4. 9.3.4 I2C
        1. 9.3.4.1 I2C Address Assignment
      5. 9.3.5 LVDS Output Termination
      6. 9.3.6 Input Termination
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Enable Control
      2. 9.4.2 Bank Input Selection
      3. 9.4.3 Bank Mute Control
      4. 9.4.4 Output Enable Control
      5. 9.4.5 Output Amplitude Selection
    5. 9.5 Programming
    6. 9.6 Register Maps
      1. 9.6.1 LMK1D1208I Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

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8 Parameter Measurement Information

GUID-7E8B5D6A-AD55-4503-8CB2-A0C973E918EE-low.gifFigure 8-1 LVDS Output DC Configuration During Device Test
GUID-20210914-SS0I-9WQM-ZDJL-4DDW6DXKSMVB-low.svgFigure 8-2 LVDS Output AC Configuration During Device Test
GUID-A261E429-9767-4BA7-B450-D467E09A000B-low.gifFigure 8-3 DC-Coupled LVCMOS Input During Device Test
GUID-ED8B2315-A708-4F25-9FA0-2AC4ABD37BFE-low.gifFigure 8-4 Output Voltage and Rise/Fall Time
GUID-772935CB-852F-41B5-A9F3-3C38EA1BB26E-low.gif
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B. Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
Figure 8-5 Output Skew and Part-to-Part Skew
GUID-E4D83546-9D23-4057-BA57-97DD4D26E425-low.gifFigure 8-6 Output Overshoot and Undershoot
GUID-5B917D0C-93FE-4D50-82DF-40E778679393-low.gifFigure 8-7 Output AC Common Mode