ZHCSCY6A June   2014  – July 2014 LMK00804B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Pin Characteristics
    2. 8.2  Absolute Maximum Ratings
    3. 8.3  Handling Ratings
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Thermal Information
    6. 8.6  Power Supply Characteristics
    7. 8.7  LVCMOS / LVTTL DC Characteristics
    8. 8.8  Differential Input DC Characteristics
    9. 8.9  Electrical Characteristics (VDDO = 3.3 V ± 5%)
    10. 8.10 Electrical Characteristics (VDDO = 2.5 V ± 5%)
    11. 8.11 Electrical Characteristics (VDDO = 1.8 V ± 0.15 V)
    12. 8.12 Electrical Characteristics (VDDO = 1.5 V ± 5%)
    13. 8.13 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
      1. 10.2.1 26
    3. 10.3 Feature Description
      1. 10.3.1 Clock Enable Timing
    4. 10.4 Device Functional Modes
      1. 10.4.1 Clock Input Function
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Output Clock Interface Circuit
    3. 11.3 Input Detail
    4. 11.4 Input Clock Interface Circuits
    5. 11.5 Typical Applications
      1. 11.5.1 Design Requirements
      2. 11.5.2 Detailed Design Procedure
      3. 11.5.3 Application Curves
        1. 11.5.3.1 System-Level Phase Noise and Additive Jitter Measurement
    6. 11.6 Do's and Don'ts
      1. 11.6.1 Power Considerations
      2. 11.6.2 Recommendations for Unused Input and Output Pins
      3. 11.6.3 Input Slew Rate Considerations
  12. 12Power Supply Recommendations
    1. 12.1 Power Supply Considerations
      1. 12.1.1 Power-Supply Filtering
      2. 12.1.2 Thermal Management
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Ground Planes
      2. 13.1.2 Power Supply Pins
      3. 13.1.3 Differential Input Termination
      4. 13.1.4 LVCMOS Input Termination
      5. 13.1.5 Output Termination
    2. 13.2 Layout Example
  14. 14器件和文档支持
    1. 14.1 器件支持
    2. 14.2 商标
    3. 14.3 静电放电警告
    4. 14.4 术语表
  15. 15机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

16 Pin
PW Package
Top View
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Pin Functions

TERMINAL TYPE(1) DESCRIPTION
NAME NUMBER
GND 1, 9, 13 G Power supply ground
OE 2 I, RPU Output enable input.

0 = Outputs in Hi-Z state

1 = Outputs in active state
VDD 3 P Power supply terminal
CLK_EN 4 I, RPU Synchronous clock enable input.

0 = Outputs are forced to logic low state

1 = Outputs are enabled with LVCMOS/LVTT levels
CLK 5 I, RPD Non-inverting differential clock input 0.
nCLK 6 I, RPD/RPU Inverting differential clock input 0. Internally biased to VDD/2 when left floating
CLK_SEL 7 I, RPU Clock select input.

0 = Select LVCMOS_CLK

1 = Select CLK, nCLK
LVCMOS_CLK 8 I, RPD Single-ended clock input. Accepts LVCMOS/LVTTL levels.
Q3, Q2, Q1, Q0 10, 12, 14, 16 O Single-ended clock outputs with LVCMOS/LVTTL levels, 7Ω output impedance
VDDO 11, 15 P Output supply terminals
(1) G = Ground, I = Input, O = Output, P = Power, RPU = 51 kΩ pullup, RPD = 51 kΩ pulldown.