SLVSIU6 March   2026 LMG1208

PRODUCT PREVIEW  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Swiching Characteristics
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Buffer Stages
      2. 6.3.2  Enable (Applicable Only to Single PWM Mode)
      3. 6.3.3  MODE Configuration
      4. 6.3.4  SYNC Output Buffer
      5. 6.3.5  Integrated PWM Logic
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Level Shifter
      8. 6.3.8  Synchronous Bootstrap
      9. 6.3.9  Output Gate drivers
      10. 6.3.10 Negative Voltage Transients
      11. 6.3.11 Dead Time/Delay Pin
      12. 6.3.12 Current Sense Amplifier
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Bias Supply Voltage
        2. 7.2.2.2 Peak Source and Sink Currents
        3. 7.2.2.3 Power Dissipation
      3. 7.2.3 Application Curves: Buck Converter
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • VEG|16
散热焊盘机械数据 (封装 | 引脚)

6.1 Overview

The LMG1208 is a floating half-bridge gate driver designed to drive N-channel MOSFETs or e-mode GaN FETs in a half-bridge configuration. The device features two input buffers, the functionality of the input buffers is dependent on the operating mode of the device set by the MODE pin. The device incorporates the PWM logic needed to drive six FET HSC converter from two incoming PWMs. DT pin configures the dead time in single PWM mode between the turn-on and turn-off transitions of the high-side and low-side FET. In all the other operating modes of the device, the DT delays the rising edge of all the PWMs, thereby inserting dead time. The floating high-side driver and low side driver is capable of operating with HB/LB voltages up to 120V, with respect to GND. A 120V synchronous bootstrap FET is integrated in the LMG1208 device to charge the high-side (HB-HS) gate drive bootstrap capacitor. Integrated robust level shifters from VDD domain to HB/LB domains are capable to operate at high speed (> 2Mhz) while consuming low power and providing clean level transitions from the control logic (VDD) domain to the floating gate drivers in HB/LB domains. Undervoltage lockout (UVLO) is provided on all three power rails: VDD, HB-HS, and LB-LS.

The LMG1208 integrates a high-voltage precise current sense amplifier that can be used for current sensing using shunt resistor or using inductor DCR method. The transconductance amplifier supports input common-mode voltage up to 35V and can be used for peak current mode control or current balancing between multiple phases. The high-side gate driver is referenced to the switch node (HS), and the low-side driver is referenced to LS. The LMG1208 floating domains provides the flexibility to the user to configure the device in synchronous buck or boost configurations by connecting LB to VDD, LS to GND on the PCB. Whereas for floating topologies such as Hybrid switched-capacitor (HSC) converter, HB and LB domains can be the gate drive domains for top and middle FETs respectively, while VDD can be the gate drive domain for the bottom FET in HSC stack.

Table 6-1 LMG1208 Highlights
FEATUREBENEFIT
3A peak source and 4A peak sink current at VDD = 5V for GaN FETs, 4.5A peak source and 5.5A peak sink current at VDD = 12V for Silicon MOSFETs High peak current capable of driving large power FETs with minimal power loss (fast-drive capability at Miller plateau)
Switch nodes HS/LS and gate driver output pins HG/LG can sustain negative transientsIncreased robustness and ability to handle undershoot and overshoot because of the PCB parasitics
120V internal synchronous boot FET to charge HB domain while LB domain completely floatingBalance between integration and cost to target various topologies such as Buck, Boost, HSC, Three Level buck, and so forth
Precise low-offset current sense amplifierReduces BOM cost and PCB space compared to other regular half-bridge gate drivers where current sensing uses external amplifier
32ns maximum propagation delay with 5ns maximum delay mismatchBest-in-class switching characteristics to reduce dead time losses and enable fast closed loop response
MODE functionalityProvides flexibility to the end application for configuring the device in different modes such as IIM (independent input mode), single PWM, HSC_HS (hybrid switched capacitor converter with high side responder), HSC_LS (hybrid switched capacitor converter with low side responder) and IIM inverted modes.
Dead time configuration via the DT pin For multiphase applications where single PWM is used per phase, dead time between high side FET and low side FET can be easily set by DT resistor to GND to avoid cross-conduction of the FETs. Even if the controller has the capability to provide two independent PWMs, DT can be used to insert dead time by shifting the rising edge of the incoming PWM- useful for applications such as HSC converter.
HSC PWM logic 48V-12V Multiphase HSC converter (total 6 FETs per HSC block) can be driven with only 2 incoming PWMs per HSC block.
Tri-state input buffersTri-state functionality can be used to turn-off the FET in fault conditions and also ensures the FET remains off at start-up where some controllers have mid-rail bias on PWM controller outputs after power-up.