SLVSIU6 March   2026 LMG1208

PRODUCT PREVIEW  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Swiching Characteristics
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Buffer Stages
      2. 6.3.2  Enable (Applicable Only to Single PWM Mode)
      3. 6.3.3  MODE Configuration
      4. 6.3.4  SYNC Output Buffer
      5. 6.3.5  Integrated PWM Logic
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Level Shifter
      8. 6.3.8  Synchronous Bootstrap
      9. 6.3.9  Output Gate drivers
      10. 6.3.10 Negative Voltage Transients
      11. 6.3.11 Dead Time/Delay Pin
      12. 6.3.12 Current Sense Amplifier
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Bias Supply Voltage
        2. 7.2.2.2 Peak Source and Sink Currents
        3. 7.2.2.3 Power Dissipation
      3. 7.2.3 Application Curves: Buck Converter
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • VEG|16
散热焊盘机械数据 (封装 | 引脚)

6.2 Functional Block Diagram

Figure 6-1 shows the functional block diagram of the LMG1208 device. The device integrates:

  • Synchronous bootstrap supply for HB-HS domain
  • Gate driver for HB and LB domain
  • Input buffer, PWM logic and control, dead time, and mode configuration block
  • Sync output buffer (useful in hybrid switched capacitor topology implementation)
  • Level shifters from VDD to HB-HS and to LB-LS domains
  • Current sense amplifier
LMG1208 LMG1208 Functional Block Diagram Figure 6-1 LMG1208 Functional Block Diagram