SLVSIU6 March   2026 LMG1208

PRODUCT PREVIEW  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Swiching Characteristics
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Buffer Stages
      2. 6.3.2  Enable (Applicable Only to Single PWM Mode)
      3. 6.3.3  MODE Configuration
      4. 6.3.4  SYNC Output Buffer
      5. 6.3.5  Integrated PWM Logic
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Level Shifter
      8. 6.3.8  Synchronous Bootstrap
      9. 6.3.9  Output Gate drivers
      10. 6.3.10 Negative Voltage Transients
      11. 6.3.11 Dead Time/Delay Pin
      12. 6.3.12 Current Sense Amplifier
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Bias Supply Voltage
        2. 7.2.2.2 Peak Source and Sink Currents
        3. 7.2.2.3 Power Dissipation
      3. 7.2.3 Application Curves: Buck Converter
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information
    3. 10.3 Mechanical Data

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • VEG|16
散热焊盘机械数据 (封装 | 引脚)

6.3.3 MODE Configuration

The LMG1208 has a MODE pin which configures the device in various operational modes. User can put a resistor from MODE pin to GND- see MODE section under Section 5.5 for resistor values. Depending on the end application and the power converter topology, MODE provides the flexibility to the LMG1208 to be used in multiple configurations.

MODE resistor cannot be changed dynamically in an application. MODE has internal current source to detect the value of the resistor connected. At the startup, MODE is sampled and device locks the operational mode. Post-that, in HSC_HS and HSC_LS modes, this terminal becomes SYNC output buffer. MODE also configures the type of input buffer and resistor structure on both the input buffers. See SYNC Output Buffer for more details.

Below function table describes the operational modes of LMG1208.

Table 6-6 MODE Setting
RMODEOperational modeDescription
Short to GNDHI LI invertedDevice inverts both the incoming PWMs on INH (HI) and INL (LI) pins. Useful for applications where some FETs (in specific topology) are to be driven in complementary fashion.
4kΩHI LIRegular use case for, for example, buck or boost converter where PWM controller provides 2 incoming PWMs.
15.8kΩSingle PWMDevice takes in single PWM and generates complementary PWM. Useful for multiphase applications where the PWM controller is only able to provide single PWM for one half-bridge phase.
54kΩHSC LS Useful for Hybrid switched capacitor converter. Device takes in two incoming PWMs from the controller and generates third PWM and drives SYNC output buffer according to this third PWM. See applications section for HSC topology implementation.
180kΩ HSC_HS
Float (Open) HI LI with boot disable Internal bootstrap path (from VDD to HB) is disabled to provide flexibility to generate bootstrap externally on PCB.
LMG1208 MODEFigure 6-2 MODE