Figure 9-16 shows a layout example of a synchronous buck regulator with discrete power MOSFETs. The design uses an inner layer as a power-loop return path directly underneath the top layer to create a low-area switching power loop. This loop area, and hence parasitic inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.

The high-frequency power loop current flows through MOSFETs, through the power ground plane on the inner layer, and back to VIN through the ceramic capacitors .

Multiple ceramic capacitors are placed in parallel close to the drain of the high-side MOSFET. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected to the inner layer ground plane with multiple vias, further minimizing parasitic loop inductance.

Additional guidelines to improve noise immunity and reduce EMI are as follows:

• Connect PGND directly to the low-side MOSFET and power ground. Connect AGND directly to an analog ground plane for sensitive analog components. The analog ground plane for AGND and the power ground plane for PGND must be connected at a single point directly under the device at the exposed pad.
• Connect the MOSFETs directly to the inductor terminal with short copper connections (without vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This event avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper pours shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI signature.
• Place the EMI filter components on the bottom side of the PCB so that the components are shielded from the power stage components on the top side.

Figure 9-16 PCB Top Layer