A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the input ripple voltage. In general, the ripple current splits between the input capacitors based on the relative impedance of the capacitors at the switching frequency.

1. Select the input capacitors with sufficient voltage and RMS ripple current ratings.
2. Use Equation 41 to calculate the input capacitor RMS ripple current assuming a worst-case duty-cycle operating point of 50%.
   Equation 41. ${\mathrm{I}}_{\mathrm{C}\mathrm{I}\mathrm{N},\mathrm{r}\mathrm{m}\mathrm{s}}=\sqrt{\mathrm{D}\times \left({{\mathrm{I}}_{\mathrm{L}\mathrm{O}\mathrm{A}\mathrm{D}}}^2\times \left(1-\mathrm{D}\right)+\frac{{∆{\mathrm{I}}_{\mathrm{L}\mathrm{O}\mathrm{U}\mathrm{T}}}^2}{12}\right)}=\sqrt{0.5\times \left(8^2\times \left(1-0.5\right)+\frac{{3.65}^2}{12}\right)}=4.1\mathrm{A}$
3. Use Equation 42 to find the required input capacitance.
   Equation 42. ${\mathrm{C}}_{\mathrm{I}\mathrm{N}}\ge \frac{\mathrm{D}\times \left(1-\mathrm{D}\right)\times {\mathrm{I}}_{\mathrm{L}\mathrm{O}\mathrm{A}\mathrm{D}}}{{\mathrm{f}}_{\mathrm{S}\mathrm{W}}\times \left(∆{\mathrm{V}}_{\mathrm{S}\mathrm{U}\mathrm{P}\mathrm{P}\mathrm{L}\mathrm{Y}}-{\mathrm{I}}_{\mathrm{L}\mathrm{O}\mathrm{A}\mathrm{D}}\times {\mathrm{R}}_{\mathrm{E}\mathrm{S}\mathrm{R}}\right)}=\frac{0.5\times \left(1-0.5\right)\times 8}{400\mathrm{k}\times \left(0.25-8\times 1\mathrm{m}\right)}=21\mathrm{\mu }\mathrm{F}$

   where

   • ΔV_SUPPLY is the input peak-to-peak ripple voltage specification.
   • R_ESR is the input capacitor ESR.
4. Recognizing the voltage coefficient of ceramic capacitors, select six 4.7µF, 100V, X7R ceramic input capacitors. Place these capacitors adjacent to the power MOSFETs.
5. Use six 10nF, 100V, X7R, 0603 ceramic capacitors near the high-side MOSFET to supply the high di/dt current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF) and low effective impedance above 100MHz. The result is lower power loop parasitic inductance, thus minimizing switch-node voltage overshoot and ringing for lower conducted and radiated EMI signature.