SNVSD17 April   2026 LM5192-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for the Serial Control Bus
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  High-Voltage Bias Supply Regulators (VCC, VDDA)
      3. 7.3.3  Enable (EN)
      4. 7.3.4  Switching Frequency
      5. 7.3.5  Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Soft Start
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Controllable On-Time
      9. 7.3.9  Dual Loop Architecture
        1. 7.3.9.1 Voltage Loop Error Amplifier
        2. 7.3.9.2 Current Loop Error Amplifier
      10. 7.3.10 Programmable ILIM
      11. 7.3.11 IOUT Monitor
      12. 7.3.12 Cable Drop Compensation
      13. 7.3.13 Slope Compensation
      14. 7.3.14 Shunt Current Sensing
      15. 7.3.15 Hiccup Mode Current Limiting
      16. 7.3.16 Device Configuration (CFG)
      17. 7.3.17 Pulse Frequency Modulation (PFM) / Synchronization
      18. 7.3.18 Thermal Shutdown (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Ready Mode
      4. 7.4.4 Active Mode
      5. 7.4.5 Sleep Mode
  9. 8 LM5192-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Powertrain Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Application
      1. 9.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Buck Inductor
          2. 9.2.1.2.2 Current-Sense Resistance
          3. 9.2.1.2.3 Output Capacitors
          4. 9.2.1.2.4 Input Capacitors
          5. 9.2.1.2.5 Compensation Components
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate-Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 LM5192-Q1 Registers

Table 8-1 lists the memory-mapped registers for the LM5192-Q1 registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.

Table 8-1 LM5192-Q1 Registers
OffsetAcronymRegister NameSection
1hOPERATIONOperation registerSection 8.1
3hCLEAR_FAULTSClear faults registerSection 8.2
21hVOUT_COMMANDSet output voltage registerSection 8.3
78hSTATUS_BYTEDevice status registerSection 8.4
79hSTATUS_WORDDevice status wordSection 8.5
D0hMFG_DEVICE_CFG_D0Set average output current limit registerSection 8.6
D1hMFG_DEVICE_CFG_D1Device configuration register 1Section 8.7
D2hMFG_DEVICE_CFG_D2Device configuration register 2Section 8.8
D5hMFG_DEVICE_CFG_D5Device configuration register 3Section 8.9
D8hMFG_DEVICE_CFG_D8Device configuration register 4Section 8.10
D9hMFG_DEVICE_CFG_D9Device configuration register 5Section 8.11

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 LM5192-Q1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1 OPERATION Register (Offset = 1h) [Reset = 00h]

OPERATION is shown in Table 8-3.

Return to the Summary Table.

Operation register is used to enable or disable the device.

Table 8-3 OPERATION Register Field Descriptions
BitFieldTypeResetDescription
7CONTROLLER_ENR/W0h Controller enable bit.
  • 0h = Disabled
  • 1h = Enabled
6-0RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.

8.2 CLEAR_FAULTS Register (Offset = 3h) [Reset = 00h]

CLEAR_FAULTS is shown in Table 8-4.

Return to the Summary Table.

Clear faults register is used to clear the fault bits in the status register 0x78h.

Table 8-4 CLEAR_FAULTS Register Field Descriptions
BitFieldTypeResetDescription
7-0CLEAR_FAULTSW0h Clear faults bit.

8.3 VOUT_COMMAND Register (Offset = 21h) [Reset = 00FAh]

VOUT_COMMAND is shown in Table 8-5.

Return to the Summary Table.

Set output voltage register is used to set the target output voltage.

Table 8-5 VOUT_COMMAND Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
11-8VOUT_MSBR/W0h Output voltage setting upper byte.
Lower limit: 3.3V (1V)
Upper limit: 48V (24V)
Step size: 20mV (10mV)
SEL_FB_DIV20 =1 (SEL_FB_DIV20 =0)
  • 0000h = 3.3V (1V)
  • 0064h = 3.3V (1V)
  • 00A5h = 3.3V (1.65V)
  • 00FAh = 5V (2.5V)
  • 01C2h = 9V (4.5V)
  • 02EEh = 15V (7.5V)
  • 03E8h = 20V (10V)
  • 0578h = 28V (14V)
  • 0708h = 36V (18V)
  • 0960h = 48V (24V)
  • FFFFh = 48V (24V)
7-0VOUT_LSBR/WFAh Output voltage setting lower byte.
Lower limit: 3.3V (1V)
Upper limit: 48V (24V)
Step size: 20mV (10mV)
SEL_FB_DIV20 =1 (SEL_FB_DIV20 =0)
  • 0000h = 3.3V (1V)
  • 0064h = 3.3V (1V)
  • 00A5h = 3.3V (1.65V)
  • 00FAh = 5V (2.5V)
  • 01C2h = 9V (4.5V)
  • 02EEh = 15V (7.5V)
  • 03E8h = 20V (10V)
  • 0578h = 28V (14V)
  • 0708h = 36V (18V)
  • 0960h = 48V (24V)
  • FFFFh = 48V (24V)

8.4 STATUS_BYTE Register (Offset = 78h) [Reset = 00h]

STATUS_BYTE is shown in Table 8-6.

Return to the Summary Table.

Device status register.

Table 8-6 STATUS_BYTE Register Field Descriptions
BitFieldTypeResetDescription
7BUSYR/W0h Device busy status bit. If set, the device is busy and unable to respond.
  • 0h = No fault
  • 1h = Fault
6OFFR/W0h Device on/off status bit. If set, the device is disabled / off.
  • 0h = No fault
  • 1h = Fault
5VOUT_OVR/W0h Device output overvoltage status bit. If set, the voltage on the device output has exceeded the set OVP threshold.
  • 0h = No fault
  • 1h = Fault
4IOUT_OCR/W0h Device output overcurrent status bit. Is set, the cycle-by-cycle current limit has been triggered.
  • 0h = No fault
  • 1h = Fault
3RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
2TEMPERATURER/W0h Device overtemperature status bit. If set, the device temperature has triggered the thermal shut down (TSD) threshold.
  • 0h = No fault
  • 1h = Fault
1CMLR/W0h Device communication, memory, or logic fault status bit. If triggered, the device memory (parity) error has occurred.
  • 0h = No fault
  • 1h = Fault
0NONE_OF_THE_ABOVER/W0h Device other fault or warning status bit. If set, a fault or warning listed in the 0x79[15:8] byte has occurred.
  • 0h = No fault
  • 1h = Fault

8.5 STATUS_WORD Register (Offset = 79h) [Reset = 0000h]

STATUS_WORD is shown in Table 8-7.

Return to the Summary Table.

Device status word.

Table 8-7 STATUS_WORD Register Field Descriptions
BitFieldTypeResetDescription
15VOUTR/W0h Device output voltage status bit. If set, the voltage on the device output has exceeded the set OVP threshold or PG OV threshold.
  • 0h = No fault
  • 1h = Fault
14IOUT_POUTR/W0h Output current or output power warning.
  • 0h = No fault
  • 1h = Fault
13RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
12CC_STATUSR/W0h Constant current (CC) status bit. If set, the device operates in CC regulation mode. Otherwise, the device operates in constant voltage (CV) regulation mode.
  • 0h = CV regulation
  • 1h = CC regulation
11nPG_STATUSR/W0h Power not good status bit. If set, the voltage on the output of the device has triggered either PG UV or PG OV threshold.
  • 0h = No fault
  • 1h = Fault
10RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
9RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
8RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
7BUSYR/W0h Device busy status bit. If set, the device is busy and unable to respond.
  • 0h = No fault
  • 1h = Fault
6OFFR/W0h Device on/off status bit. If set, the device is disabled / off.
  • 0h = No fault
  • 1h = Fault
5VOUT_OVR/W0h Device output overvoltage status bit. If set, the voltage on the device output has exceeded the set OVP threshold.
  • 0h = No fault
  • 1h = Fault
4IOUT_OCR/W0h Device output overcurrent status bit. Is set, the cycle-by-cycle current limit has been triggered.
  • 0h = No fault
  • 1h = Fault
3RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
2TEMPERATURER/W0h Device overtemperature status bit. If set, the device temperature has triggered the thermal shut down (TSD) threshold.
  • 0h = No fault
  • 1h = Fault
1CMLR/W0h Device communication, memory, or logic fault status bit. If triggered, the device memory (parity) error has occurred.
  • 0h = No fault
  • 1h = Fault
0NONE_OF_THE_ABOVER/W0h Device other fault or warning status bit. If set, a fault or warning listed in the 0x79[15:8] byte has occurred.
  • 0h = No fault
  • 1h = Fault

8.6 MFG_DEVICE_CFG_D0 Register (Offset = D0h) [Reset = 0Ah]

MFG_DEVICE_CFG_D0 is shown in Table 8-8.

Return to the Summary Table.

Set average output current limit register.

Table 8-8 MFG_DEVICE_CFG_D0 Register Field Descriptions
BitFieldTypeResetDescription
7-0AVG_ILIM_THRESHOLDR/WAh Set average output current limit threshold. Assumes 8mΩ (2mΩ) sense resistor is selected.
Lower limit: 0.5A (2A)
Upper limit: 7.5A (30A)
Step size: 50mA (200mA)
  • 0h = 0.5A (2A)
  • Ah = 0.5A (2A)
  • 3Ch = 3A (12A)
  • 64h = 5A (20A)
  • 96h = 7.5A (30A)
  • FFh = 7.5A (30A)

8.7 MFG_DEVICE_CFG_D1 Register (Offset = D1h) [Reset = 8Ah]

MFG_DEVICE_CFG_D1 is shown in Table 8-9.

Return to the Summary Table.

Device configuration register 1 is used to select FB divider, configure DRSS function, set the switching frequency, and select compensation for the constant current loop.

Table 8-9 MFG_DEVICE_CFG_D1 Register Field Descriptions
BitFieldTypeResetDescription
7SEL_FB_DIV20R/W1h Select FB divider. The selection determines the output voltage range and step size.
  • 0h = DIV10 (10mV step size, 1V-24V range)
  • 1h = DIV20 (20mV step size, 3.3V-48V range)
6DRSS_ENR/W0h Enable DRSS function.
  • 0h = DRSS disabled
  • 1h = DRSS enabled
5DRSS_FMODR/W0h Select DRSS triangular modulation frequency.
  • 0h = 10kHz
  • 1h = 2.5kHz
4-3FREQR/W1h Select switching frequency.
  • 0h = 200kHz
  • 1h = 400kHz
  • 2h = 600kHz
  • 3h = 2.2MHz
2-1CC_COMPR/W1h Select CC compensation time constant.
  • 0h = 0.1ms
  • 1h = 0.2ms
  • 2h = 0.3ms
  • 3h = 0.4ms
0RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.

8.8 MFG_DEVICE_CFG_D2 Register (Offset = D2h) [Reset = CBh]

MFG_DEVICE_CFG_D2 is shown in Table 8-10.

Return to the Summary Table.

Device configuration register 2 is used to configure output active discharge, output voltage slew rate, and select soft-start time.

Table 8-10 MFG_DEVICE_CFG_D2 Register Field Descriptions
BitFieldTypeResetDescription
7ACTIVE_DISCHARGE_CFG1R/W1h Enable active discharge during VOUT high to low transition.
  • 0h = Disabled
  • 1h = Enabled
6ACTIVE_DISCHARGE_CFG2R/W1h Enable active discharge during PFM to FPWM transition.
  • 0h = Disabled
  • 1h = Enabled
5ACTIVE_DISCHARGE_CFG3R/W0h Enable continuous active discharge.
  • 0h = Disabled
  • 1h = Enabled
4-3VOUT_SLEW_RATER/W1h Select output voltage slew rate.
SEL_FB_DIV20 =1 (SEL_FB_DIV20 =0)
  • 0h = 40mV/us (20mV/us)
  • 1h = 20mV/us (10mV/us)
  • 2h = 1mV/us (0.5mV/us)
  • 3h = 0.5mV/us (0.25mV/us)
2-1ACTIVE_DISCHARGE_STRENGTHR/W1h Select active discharge strength.
  • 0h = Disabled
  • 1h = 25mA
  • 2h = 50mA
  • 3h = 75mA
0SOFT_START_TIMER/W1h Select soft-start ramp time.
  • 0h = 5V/ms
  • 1h = 2.5V/ms

8.9 MFG_DEVICE_CFG_D5 Register (Offset = D5h) [Reset = 65h]

MFG_DEVICE_CFG_D5 is shown in Table 8-11.

Return to the Summary Table.

Device configuration register 3 is used to enable and configure overvoltage protection (OVP) function and set OVP thresholds.

Table 8-11 MFG_DEVICE_CFG_D5 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned.
6OVP_ENR/W1h Enable OVP detection.
  • 0h = Disabled
  • 1h = Enabled
5OVP_CFGR/W1h Configure OVP detection.
  • 0h = OVP detection only results in the Status register update
  • 1h = OVP detection interrupts switching, discharges VOUT, sets the VOUT_OV bit in the Status register
4-0OVP_THRESHOLDR/W5h Select OVP rising threshold.
Lower limit: 105%
Upper limit: 136%
Step size: 1%
  • 0h = 105%
  • 5h = 110%
  • Ah = 115%
  • 1Fh = 136%

8.10 MFG_DEVICE_CFG_D8 Register (Offset = D8h) [Reset = CAh]

MFG_DEVICE_CFG_D8 is shown in Table 8-12.

Return to the Summary Table.

Device configuration register 4 is used to set the NINT mask, enable a connection from the VCC and VDD regulator inputs to the VOUTF pin, enable and configure gain of the cable drop compensation function.

Table 8-12 MFG_DEVICE_CFG_D8 Register Field Descriptions
BitFieldTypeResetDescription
7NINT_MASKR/W1h Mask NINT for all STATUS register bits except the CC_STATUS bit.
  • 0h = NINT for most STATUS BYTE/WORD faults.
  • 1h = NINT for only MFG_SPECIFIC bit (CC regulation) in the STATUS register
6BIAS_ENR/W1h Enable connection from the VDD and VCC regulator bias inputs to the VOUTF pin.
  • 0h = Disabled
  • 1h = Enabled
5CDC_ENR/W0h Enable cable drop compensation.
  • 0h = Disabled
  • 1h = Enabled
4-0CDC_GAINR/WAh Configure CDC gain.
Lower limit: 0V/V
Upper limit: 62V/V
Step size: 2V/V
  • 0h = 0V/V
  • 1h = 2V/V
  • Ah = 20V/V
  • 1Fh = 62V/V

8.11 MFG_DEVICE_CFG_D9 Register (Offset = D9h) [Reset = 00h]

MFG_DEVICE_CFG_D9 is shown in Table 8-13.

Return to the Summary Table.

Device configuration register 5 is used to enable MFI function, enable HICCUP mode, override mode selection of the PFM pin, select MODE, and power good (PG) detection window.

Table 8-13 MFG_DEVICE_CFG_D9 Register Field Descriptions
BitFieldTypeResetDescription
7MFI_ENR/W0h Enable MFI CC regulation (1.6xILIM for the 1ms of CC regulation).
  • 0h = Disabled
  • 1h = Enabled
6HICCUP_ENR/W0h Enable HICCUP operation.
  • 0h = Disabled
  • 1h = Enabled
5OVERRIDE_PFMR/W0h Override PFM pin setting.
  • 0h = PFM pin sets the mode of operation
  • 1h = MODE bit sets the mode of operation
4MODER/W0h Select mode of operation.
  • 0h = FPWM
  • 1h = PFM
3PG_10PCTR/W0h Select PG window.
  • 0h = 5%
  • 1h = 10%
2SPARE2R/W0h Spare bit#2
  • 0h = Disabled
  • 1h = Enabled
1SPARE1R/W0h Spare bit#1
  • 0h = Disabled
  • 1h = Enabled
0SPARE0R/W0h Spare bit#0
  • 0h = Disabled
  • 1h = Enabled