ZHCSQO1D june   2022  – august 2023 LM5177

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Gate Driver Rise Time and Fall Time
    2. 7.2 Gate Driver Dead (Transition) Time
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On Reset (POR System)
      2. 8.3.2  Buck-Boost Control Scheme
        1. 8.3.2.1 Boost Mode
        2. 8.3.2.2 Buck Mode
        3. 8.3.2.3 Buck-Boost Mode
      3. 8.3.3  Power Save Mode
      4. 8.3.4  Supply Voltage Selection – VMAX Switch
      5. 8.3.5  Enable and Undervoltage Lockout
      6. 8.3.6  Oscillator Frequency Selection
      7. 8.3.7  Frequency Synchronization
      8. 8.3.8  Voltage Regulation Loop
      9. 8.3.9  Output Voltage Tracking
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Configurable Soft Start
      12. 8.3.12 Peak Current Sensor
      13. 8.3.13 Current Monitoring and Current Limit Control Loop
      14. 8.3.14 Short Circuit - Hiccup Protection
      15. 8.3.15 nFLT Pin and Protections
      16. 8.3.16 Device Configuration Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Slope Compensation
        6. 9.2.2.6  Output Capacitor
        7. 9.2.2.7  Input Capacitor
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Frequency Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Bi-Directional Power Backup
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Driver Layout
      3. 11.1.3 Controller Layout
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design with WEBENCH Tools
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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8.3.12 Peak Current Sensor

The integrated peak current sensor enables a low inductive sensing as it is located in series with the main inductor. It also can monitor the peak inductor current under all operation modes (boost, buck-boost and buck ) as well as for both current directions i.e. the bi-directional operation.

As the integrated sensor supports high bandwidth signals a differential mode filter adopted to the selected switching frequency is recommended for best performance. For most applications we recommend a resistor value for R(DIFF1/2) of 100 Ω. You can use the equation below to determine the filter capacitor:

Equation 15. C ( D I F F ) =   1 2 π ∙ ( R ( D I F F 1 ) + R ( D I F F 2 ) )   ∙ 5 f s w

Where the lowest corner frequency for the differential filter should be five times the selected switching frequency.

For input voltages above 40V it is recommended to place additional filter capacitors between the filter resistor to GND. For most tested applications and PCB's a value of 47 pF for C(COMM1/2) and achieved sufficient suppression of the common mode switching noise for the current sensor. The above boundaries are determined with suitable applicative PCB and multiple device units during a start-up into the current limit.

Current sense resistors consist a parasitic inductance based on their geometry and the selected component vendors design. If the desired application requires high currents the impact of the external component parasitic can be reduced by placing multiple sense resistors in parallel.

GUID-20230419-SS0I-J31F-7SJK-HHC3H0VRWWKF-low.gif Figure 8-16 Simplified Schematic of the peak current sensor

The low and accurate peak current sense threshold of 50 mV (typ.) enables a power stage design with small losses over the external sense resistor and a small deviation of the inductor saturation current relative to the average inductor current. Although if there is noise coupling on the PCB or injected to the device a reaction of an increase output ripple caused by a neg. current spike in the inductor are observed. If this behavior (see Figure 8-17 ) is not suppressed by

The negative inductor current build up can be predicted by a maximum of 3 switching cycles with the following equation:

Equation 16. I ( p e a k , n e g ) = 3 f s w ( V O - V I ) L
GUID-20230510-SS0I-ZL3T-LJFL-G0HS4JJKFB6S-low.gif Figure 8-17 Timing diagram of an example for a negative inductor current spike