When CLR is high, and the output is not in a latched condition, the comparator is armed and ready to respond to next high-to-low output condition to latch.

The CLR input clears the output latch on the high-to-low (falling) edge of the CLR input.

If CLR is held low, the comparator is in "Transparent" mode and the output continues to respond to input conditions. See Section 6.4.2.2.

The latch is armed when the CLR input returns to high and awaits the next high-to-low output transition.

During the short CLR pulse to clear the latch, there is a possibility that the output transitions during the time the latch is being reset if the inputs are crossing. The CLR reset pulse must be as short as possible for the system to prevent false pulses. The recommended minimum CLR pulse is 200ns.

There can be a setup-time contention if the CLR pin is transitioning (falling) at the same time as the comparator output transitions. The output state is indeterminate during the CLR falling edge time. The recommendation is to make the CLR falling-edge as fast as possible to avoid this contention (<100ns fall time).

The CLR pin is a Failsafe input, accepting logic high levels up to 36V, independent of the comparator supply voltage. The 0.6V maximum threshold accepts digital logic level inputs from 15V CMOS, to low voltage TTL, to 1.2V CMOS logic.

Floating the CLR input is not recommended. If "normal", "unlatched" mode is desired, tie that channels CLR input to V-.

Thought must be taken as to if an external pull-up or pull-down resistor is required on the CLR pin to make sure the CLR pin is in the proper state during start-up when the controller output is Hi-Z during controller initialization. The controller must initialize the GPIO pin as soon as possible after start-up.