ZHCSCL3 JUNE   2014 DS90UH925AQ-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Electrical Characteristics
    6. 7.6  AC Electrical Characteristics
    7. 7.7  Recommended Timing for the Serial Control Bus
    8. 7.8  DC and AC Serial Control Bus Characteristics
    9. 7.9  AC Timing Diagrams and Test Circuits
    10. 7.10 Switching Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Functional Block Diagram
      2. 8.1.2 Feature Description
        1. 8.1.2.1  High Speed Forward Channel Data Transfer
        2. 8.1.2.2  Low Speed Back Channel Data Transfer
        3. 8.1.2.3  Common Mode Filter Pin (CMF)
        4. 8.1.2.4  Video Control Signal Filter
        5. 8.1.2.5  Backward Compatible Mode
        6. 8.1.2.6  EMI Reduction Features
          1. 8.1.2.6.1 Input SSC Tolerance (SSCT)
        7. 8.1.2.7  LVCMOS VDDIO Option
        8. 8.1.2.8  Power Down (PDB)
        9. 8.1.2.9  Remote Auto Power Down Mode
        10. 8.1.2.10 Input PCLK Loss Detect
        11. 8.1.2.11 Serial Link Fault Detect
        12. 8.1.2.12 Pixel Clock Edge Select (RFB)
        13. 8.1.2.13 Low Frequency Optimization (LFMODE)
        14. 8.1.2.14 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
        15. 8.1.2.15 GPIO[3:0] and GPO_REG[7:4]
        16. 8.1.2.16 I2S Transmitting
          1. 8.1.2.16.1 Secondary I2S Channel
          2. 8.1.2.16.2 HDCP
      3. 8.1.3 Built In Self Test (BIST)
        1. 8.1.3.1 BIST Configuration and Status
        2. 8.1.3.2 Forward Channel and Back Channel Error Checking
      4. 8.1.4 Internal Pattern Generation
      5. 8.1.5 Change Summary from DS90UH925Q
    2. 8.2 Device Functional Modes
      1. 8.2.1 Configuration Select (MODE_SEL)
      2. 8.2.2 HDCP Repeater
        1. 8.2.2.1 Repeater Configuration
        2. 8.2.2.2 Repeater Connections
    3. 8.3 Programming
      1. 8.3.1 Serial Control Bus
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Typical Application Connection
        2. 9.2.2.2 Power Up Requirements and PDB Pin
        3. 9.2.2.3 CML Interconnect Guidelines
        4. 9.2.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DS90UH925AQ Pin Diagram
48 Pins
Top View
po_snls481.gif

Pin Functions

PIN NAME PIN # I/O, TYPE DESCRIPTION
LVCMOS PARALLEL INTERFACE
R[7:0] 34, 33, 32, 29, 28, 27, 26, 25 I, LVCMOS
w/ pull down 		RED Parallel Interface Data Input Pins
Leave open if unused
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1.
G[7:0] 42, 41, 40, 39, 38, 37, 36, 35 I, LVCMOS
w/ pull down 		GREEN Parallel Interface Data Input Pins
Leave open if unused
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
B[7:0] 2, 1, 48, 47, 46, 45, 44, 43 I, LVCOS
w/ pull down		 BLUE Parallel Interface Data Input Pins
Leave open if unused
B0 can optionally be used as GPO_REG4 and B1 can optionally be used as GPO_REG5.
HS 3 I, LVCMOS
w/ pull down 		Horizontal Sync Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6
VS 4 I, LVCMOS
w/ pull down		 Vertical Sync Input Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs.
DE 5 I, LVCMOS
w/ pull down 		Data Enable Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6
PCLK 10 I, LVCMOS
w/ pull down		 Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6
I2S_CLK, I2S_WC, I2S_DA 13, 12, 11 I, LVCMOS
w/ pull down		 Digital Audio Interface Data Input Pins
Leave open if unused
I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
OPTIONAL PARALLEL INTERFACE
I2S_DB 44 I, LVCMOS
w/ pull down		 Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by MODE_SEL pin or configuration register
Leave open if unused
I2S_DB can optionally be used as B1 or GPO_REG5.
GPIO[3:0] 36, 35, 26, 25 I/O, LVCMOS
w/ pull down		 General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or configuration register. See Table 6
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[7:4] 12, 11, 44, 43 O, LVCMOS
w/ pull down		 General Purpose Outputs and set by configuration register. See Table 6
Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
CONTROL
PDB 21 I, LVCMOS
w/ pull-down		 Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL 24 I, Analog Device Configuration Select. See Table 4
I2C
IDx 6 I, Analog I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 20
SCL 8 I/O, LVCMOS
Open Drain		 I2C Clock Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
SDA 9 I/O, LVCMOS
Open Drain		 I2C Data Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
STATUS
INTB 31 O, LVCMOS
Open Drain		 Interrupt. Read ISR register to determine source. Interrupt clears on ISR read.
INTB = H, normal
INTB = L, Interrupt request
Recommended pull-up: 4.7 kΩ to VDDIO
REM_INTB 16 O, LVCMOS Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB will be driven LOW until lock is achieved with the downstream serializer.
REM_INTB = H, normal
REM_INTB = L, interrupt request
FPD-Link III SERIAL INTERFACE
DOUT+ 20 O, LVDS True Output
The output must be AC-coupled with a 0.1µF capacitor.
DOUT- 19 O, LVDS Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
CMF 23 Analog Common Mode Filter.
Connect 0.1µF to GND
POWER(1) and GROUND
VDD33 22 Power Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND
VDDIO 30 Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPHS12, CAPP12 17, 14 CAP Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each CAP pin.
CAPL12 7 CAP Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this CAP pin.
OTHERS
RES[1:0] 18, 15 GND Reserved. Tie to Ground.
(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. Refer to Power Up Requirements and PDB Pin for details.