ZHCSGW1D september   2017  – march 2023 DS90UB953-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended Timing for the Serial Control Bus
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CSI-2 Receiver
        1. 7.3.1.1 CSI-2 Receiver Operating Modes
        2. 7.3.1.2 CSI-2 Receiver High-Speed Mode
        3. 7.3.1.3 CSI-2 Protocol Layer
        4. 7.3.1.4 CSI-2 Short Packet
        5. 7.3.1.5 CSI-2 Long Packet
        6. 7.3.1.6 CSI-2 Errors and Detection
          1. 7.3.1.6.1 CSI-2 ECC Detection and Correction
          2. 7.3.1.6.2 CSI-2 Check Sum Detection
          3. 7.3.1.6.3 D-PHY Error Detection
          4. 7.3.1.6.4 CSI-2 Receiver Status
      2. 7.3.2 FPD-Link III Forward Channel Transmitter
        1. 7.3.2.1 Frame Format
      3. 7.3.3 FPD-Link III Back Channel Receiver
      4. 7.3.4 Serializer Status and Monitoring
        1. 7.3.4.1 Forward Channel Diagnostics
        2. 7.3.4.2 Back Channel Diagnostics
        3. 7.3.4.3 Voltage and Temperature Sensing
          1. 7.3.4.3.1 Programming Example
        4. 7.3.4.4 Built-In Self Test
      5. 7.3.5 FrameSync Operation
        1. 7.3.5.1 External FrameSync
        2. 7.3.5.2 Internally Generated FrameSync
      6. 7.3.6 GPIO Support
        1. 7.3.6.1 GPIO Status
        2. 7.3.6.2 GPIO Input Control
        3. 7.3.6.3 GPIO Output Control
        4. 7.3.6.4 Forward Channel GPIO
        5. 7.3.6.5 Back Channel GPIO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
        1. 7.4.1.1 Synchronous Mode
        2. 7.4.1.2 Non-Synchronous Clock Mode
        3. 7.4.1.3 Non-Synchronous Internal Mode
        4. 7.4.1.4 DVP Backwards Compatibility Mode
        5. 7.4.1.5 Configuring CLK_OUT
      2. 7.4.2 MODE
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Configuration
        1. 7.5.1.1 CLK_OUT/IDX
          1. 7.5.1.1.1 IDX
      2. 7.5.2 I2C Interface Operation
      3. 7.5.3 I2C Timing
    6. 7.6 Pattern Generation
      1. 7.6.1 Reference Color Bar Pattern
      2. 7.6.2 Fixed Color Patterns
      3. 7.6.3 Packet Generator Programming
        1. 7.6.3.1 Determining Color Bar Size
      4. 7.6.4 Code Example for Pattern Generator
    7. 7.7 Register Maps
      1. 7.7.1  I2C Device ID Register
      2. 7.7.2  Reset
      3. 7.7.3  General Configuration
      4. 7.7.4  Forward Channel Mode Selection
      5. 7.7.5  BC_MODE_SELECT
      6. 7.7.6  PLL Clock Control
      7. 7.7.7  Clock Output Control 0
      8. 7.7.8  Clock Output Control 1
      9. 7.7.9  Back Channel Watchdog Control
      10. 7.7.10 I2C Control 1
      11. 7.7.11 I2C Control 2
      12. 7.7.12 SCL High Time
      13. 7.7.13 SCL Low Time
      14. 7.7.14 Local GPIO DATA
      15. 7.7.15 GPIO Input Control
      16. 7.7.16 DVP_CFG
      17. 7.7.17 DVP_DT
      18. 7.7.18 Force BIST Error
      19. 7.7.19 Remote BIST Control
      20. 7.7.20 Sensor Voltage Gain
      21. 7.7.21 Sensor Control 0
      22. 7.7.22 Sensor Control 1
      23. 7.7.23 Voltage Sensor 0 Thresholds
      24. 7.7.24 Voltage Sensor 1 Thresholds
      25. 7.7.25 Temperature Sensor Thresholds
      26. 7.7.26 CSI-2 Alarm Enable
      27. 7.7.27 Alarm Sense Enable
      28. 7.7.28 Back Channel Alarm Enable
      29. 7.7.29 CSI-2 Polarity Select
      30. 7.7.30 CSI-2 LP Mode Polarity
      31. 7.7.31 CSI-2 High-Speed RX Enable
      32. 7.7.32 CSI-2 Low Power Enable
      33. 7.7.33 CSI-2 Termination Enable
      34. 7.7.34 CSI-2 Packet Header Control
      35. 7.7.35 Back Channel Configuration
      36. 7.7.36 Datapath Control 1
      37. 7.7.37 Remote Partner Capabilities 1
      38. 7.7.38 Partner Deserializer ID
      39. 7.7.39 Target 0 ID
      40. 7.7.40 Target 1 ID
      41. 7.7.41 Target 2 ID
      42. 7.7.42 Target 3 ID
      43. 7.7.43 Target 4 ID
      44. 7.7.44 Target 5 ID
      45. 7.7.45 Target 6 ID
      46. 7.7.46 Target 7 ID
      47. 7.7.47 Target 0 Alias
      48. 7.7.48 Target 1 Alias
      49. 7.7.49 Target 2 Alias
      50. 7.7.50 Target 3 Alias
      51. 7.7.51 Target 4 Alias
      52. 7.7.52 Target 5 Alias
      53. 7.7.53 Target 6 Alias
      54. 7.7.54 Target 7 Alias
      55. 7.7.55 Back Channel Control
      56. 7.7.56 Revision ID
      57. 7.7.57 Device Status
      58. 7.7.58 General Status
      59. 7.7.59 GPIO Pin Status
      60. 7.7.60 BIST Error Count
      61. 7.7.61 CRC Error Count 1
      62. 7.7.62 CRC Error Count 2
      63. 7.7.63 Sensor Status
      64. 7.7.64 Sensor V0
      65. 7.7.65 Sensor V1
      66. 7.7.66 Sensor T
      67. 7.7.67 CSI-2 Error Count
      68. 7.7.68 CSI-2 Error Status
      69. 7.7.69 CSI-2 Errors Data Lanes 0 and 1
      70. 7.7.70 CSI-2 Errors Data Lanes 2 and 3
      71. 7.7.71 CSI-2 Errors Clock Lane
      72. 7.7.72 CSI-2 Packet Header Data
      73. 7.7.73 Packet Header Word Count 0
      74. 7.7.74 Packet Header Word Count 1
      75. 7.7.75 CSI-2 ECC
      76. 7.7.76 IND_ACC_CTL
      77. 7.7.77 IND_ACC_ADDR
      78. 7.7.78 IND_ACC_DATA
      79. 7.7.79 FPD3_TX_ID0
      80. 7.7.80 FPD3_TX_ID1
      81. 7.7.81 FPD3_TX_ID2
      82. 7.7.82 FPD3_TX_ID3
      83. 7.7.83 FPD3_TX_ID4
      84. 7.7.84 FPD3_TX_ID5
      85. 7.7.85 Indirect Access Registers
        1. 7.7.85.1  PGEN_CTL
        2. 7.7.85.2  PGEN_CFG
        3. 7.7.85.3  PGEN_CSI_DI
        4. 7.7.85.4  PGEN_LINE_SIZE1
        5. 7.7.85.5  PGEN_LINE_SIZE0
        6. 7.7.85.6  PGEN_BAR_SIZE1
        7. 7.7.85.7  PGEN_BAR_SIZE0
        8. 7.7.85.8  PGEN_ACT_LPF1
        9. 7.7.85.9  PGEN_ACT_LPF0
        10. 7.7.85.10 PGEN_TOT_LPF1
        11. 7.7.85.11 PGEN_TOT_LPF0
        12. 7.7.85.12 PGEN_LINE_PD1
        13. 7.7.85.13 PGEN_LINE_PD0
        14. 7.7.85.14 PGEN_VBP
        15. 7.7.85.15 PGEN_VFP
        16. 7.7.85.16 PGEN_COLOR0
        17. 7.7.85.17 PGEN_COLOR1
        18. 7.7.85.18 PGEN_COLOR2
        19. 7.7.85.19 PGEN_COLOR3
        20. 7.7.85.20 PGEN_COLOR4
        21. 7.7.85.21 PGEN_COLOR5
        22. 7.7.85.22 PGEN_COLOR6
        23. 7.7.85.23 PGEN_COLOR7
        24. 7.7.85.24 PGEN_COLOR8
        25. 7.7.85.25 PGEN_COLOR9
        26. 7.7.85.26 PGEN_COLOR10
        27. 7.7.85.27 PGEN_COLOR11
        28. 7.7.85.28 PGEN_COLOR12
        29. 7.7.85.29 PGEN_COLOR13
        30. 7.7.85.30 PGEN_COLOR14
        31. 7.7.85.31 PGEN_COLOR15
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-over-Coax
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 CSI-2 Interface
        2. 8.2.2.2 FPD-Link III Input / Output
        3. 8.2.2.3 Internal Regulator Bypassing
        4. 8.2.2.4 Loop Filter Decoupling
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
      1. 9.1.1 System Initialization
    2. 9.2 Power Down (PDB)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CSI-2 Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwisespecified.
PARAMETERTEST CONDITIONSPIN OR FREQUENCYMINTYPMAXUNIT
POWER CONSUMPTION
IDD_TOTALSupply current416-MHz CSI Input Clock, 4 Lane Mode, Checkerboard PatternVDDPLL, VDDD, VDDDRV160225mA
IDDPLLVDDPLL5580
IDDDVDDD4570
IDDDRVVDDDRV6075
1.8-V LVCMOS I/O (VDD) = 1.71 V to 1.89 V)
VOHHigh level output voltageIOH = –4 mAGPIO[3:0], CLK_OUTV(VDD) – 0.45V(VDD)V
VOLLow level output voltageIOL = +4 mAGPIO[3:0], CLK_OUTGND0.45V
VIHHigh level input voltageGPIO[3:0], PDB, CLKINV(VDD) × 0.65V(VDD)V
VILLow level input voltageGPIO[3:0], PDB, CLKINGNDV(VDD) × 0.35V
IIHInput high currentVIN = V(VDD)GPIO[3:0], PDB, CLKIN20µA
IILInput low currentVIN = GNDGPIO[3:0], PDB, CLKIN-20µA
IOSOutput short-circuit currentVOUT = 0 V-36mA
IOZTRI-STATE output currentVOUT = V(VDD), VOUT = GNDGPIO[3:0], CLK_OUT±20µA
CINInput capacitance5pF
FPD-LINK III INPUT/OUTPUT
VIN-BCSingle-ended input voltageCoaxial configuration, 50 Ω, maximum cable lengthDOUT+, DOUT-120mV
VID-BCDifferential input voltageSTP configuration, 100 Ω, maximum cable lengthDOUT+, DOUT-240
EH-FCForward channel eye heightCoaxial configuration, FPD-Link forward channel = 4.16 GbpsDOUT+, DOUT-425mVp-p
STP configuration, FPD-Link forward channel = 4.16 GbpsDOUT+, DOUT-850
tTR-FCForward channel output transition timeFPD-Link forward channel = 4.16Gbps;  20% to 80%DOUT+, DOUT-65ps
tJIT-FCForward channel output jitterSynchronous mode, measured with f/15 –3dB CDR Loop BWDOUT+, DOUT-0.21UI
Non-synchronous mode, measured with f/15 –3dB CDR Loop BWDOUT+, DOUT-0.22
fREFInternal reference frequencyNon-synchronous internal clocking mode24.225.5MHz
FPD-LINK III DRIVER SPECIFICATIONS (DIFFERENTIAL)
VODp-pOutput differential voltageRL = 100 ΩDOUT+, DOUT-104011501340mVp-p
ΔVODOutput voltage imbalanceDOUT+, DOUT-524mV
VOSOutput differential offset voltageDOUT+, DOUT-575mV
ΔVOSOffset voltage imbalanceDOUT+, DOUT-2mV
IOSOutput short-circuit currentDOUT = 0 VDOUT+, DOUT-–22mA
RTInternal termination resistanceBetween DOUT+ and DOUT-DOUT+, DOUT-80100120Ω
FPD-LINK III DRIVER SPECIFICATIONS (SINGLE-ENDED)
VOUTOutput single-ended voltageRL = 50 ΩDOUT+, DOUT-520575670mVp-p
IOSOutput short-circuit currentDOUT = 0 VDOUT+, DOUT-–22mA
RTSingle-ended termination resistanceDOUT+, DOUT-405060Ω
VOLTAGE AND TEMPERATURE SENSING
VACCVoltage accuracySeeVoltage and Temperature SensingGPIO[1:0]±1LSB
TACCTemperature accuracySeeVoltage and Temperature Sensing±1LSB
CSI-2 HS INTERFACE DC SPECIFICATIONS
VCMRX(DC)Common-mode voltage HS receive modeCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		70330mV
VIDTHDifferential input high thresholdCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		70mV
VIDTLDifferential input low thresholdCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		–70mV
ZIDDifferential input impedanceCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		80100125Ω
CSI-2 HS INTERFACE AC SPECIFICATIONS
tHOLDData to clock setup timeCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		0.15UI
tSETUPData to clock hold timeCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		0.15UI
CSI-2 LP INTERFACE DC SPECIFICATIONS
VIHLogic high input voltageCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		880790mV
VILLogic low input voltageCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		710550mV
VHYSTInput hysteresisCSI_D3P/N, CSI_D2P/N,
CSI_D1P/N, CSI_D0P/N,
CSI_CLKP/N		2575mV
LVCMOS I/O
tCLHLVCMOS low-to-high transition timeV(VDD) = 1.71 to 1.89 VGPIO[3:0]2ns
tCHLLVCMOS high-to-low transition timeV(VDD) = 1.71 to 1.89 VGPIO[3:0]2ns
tPDBPDB reset pulse widthVoltage supplies applied and stablePDB3ms
SERIAL CONTROL BUS
VIHInput high levelI2C_SCL, I2C_SDA0.7 × V(I2C)V(I2C)mV
VILInput low levelI2C_SCL, I2C_SDAGND0.3 × V(I2C)mV
VHYInput hysteresisI2C_SCL, I2C_SDA>50mV
VOLOutput low levelV(I2C) < 2 V,  IOL = 3 mA, Standard-mode/Fast-modeI2C_SCL, I2C_SDA00.2 × V(I2C)V
V(I2C) < 2 V,  IOL = 20 mA, Fast-mode plusI2C_SCL, I2C_SDA00.2 × V(I2C)V
V(I2C) > 2 V,  IOL = 3 mA, Standard-mode/Fast-modeI2C_SCL, I2C_SDA00.4V
V(I2C) > 2 V,  IOL = 20 mA, Fast-mode plusI2C_SCL, I2C_SDA00.4V
IIHInput high currentVIN = V(I2C)I2C_SCL, I2C_SDA-1010µA
IILInput low currentVIN = 0 VI2C_SCL, I2C_SDA-1010µA
IILInput low currentVIN = 0 VI2C_SCL, I2C_SDA-1010µA
CINInput capacitanceI2C_SCL, I2C_SDA5pf