7.3.1 Device Data Path Operation

The DS125DF1610 data path consists of several key blocks as shown in Figure 2. These key circuits are:

• AC-coupled Receiver with Signal Detect
• CTLE
• Cross Point Switch
• DFE with VGA
• CDR
• Differential Driver with FIR Filter

7.3.2 AC-Coupled Receiver with Signal Detect

The differential receiver for each DS125DF1610 channel contains on chip AC coupling capacitors. The minimum bandwidth for this AC coupled receiver is 16kHz. The receiver also contains a signal detect circuit.

The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to automatically power on or off the rest of the high speed data path depending on if a signal is present. The signal detect block can be manually controlled in the SMBus channel registers. This can be useful if it is desired manually force channels to be disabled. For information on how to manually operate the signal detect circuit please see the DS125DF1610 Programming Guide and channel register 0x14 information.

7.3.3 CTLE

The CTLE in the DS125DF1610 is a fully adaptive equalizer with adjustable bandwidth and optional limiting stage. The CTLE adapts according to a Figure of Merit (FOM) calculation during the lock acquisition process. Once the CDR has locked and the CTLE has been adapted, the CTLE boost level will be frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state. The CTLE is typically re-adapted by resetting the CDR, set and then clear channel register 0x0A[3:2].

The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost settings. Users also have the option of limiting the EQ table length to any value between a minimum value of 1 and a maximum value of 32.

CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost combinations that sum to the same number will have approximately the same boost level, but will result in a different shape for the EQ transfer function (boost curve). The boost levels can be set between 0 dB and 31 dB.

The CTLE bandwidth can be adjusted through SMBus control to 3 different levels:

The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather than a linear stage. This is useful in some applications, but it should not be typically used in combination with the DFE.

7.3.4 Cross Point Switch

Each quad has a 4x4 non-blocking analog cross point switch. This allows for full switching or broadcasting of data between any input within the quad to any output within the quad. Since the cross point switch is an analog implementation, all of the channels are allowed to operate asynchronously. The analog implementation also minimizes added latency through the device.

As shown in Figure 3, the cross point switch connections for each quad are located between CTLE and DFE in each channel.

The cross point switch consists of 4 sets of MUXs and buffers. In each channel there is a local buffer and a multi-drive buffer. The local buffer transmits data from the CTLE to the DFE of the same channel. The multi drive buffer transmits data from the CTLE to the DFE(s) of other channels within the quad. Each channel has two MUXs:

1. Data path mux – Selects whether to get data from the local buffer or from the other channel’s multi-driver buffer
2. Control bus mux – Selects where the signal detect and EQ control bus should be connected. This setting should mirror the data path mux setting. Note, when an EQ is connected to another channel’s CDR the EQ becomes associated with that CDR’s register set. For example, if the cross point was configured to do point to point switching from the inputs of channel 0 to the output of channel 1 and the inputs of channel 1 to the outputs of channel 0, the EQ physically located at the pins for inputs of channel 0 would be accessible through the register set of channel 1.

A simplified diagram of the cross point switch is shown in Figure 3.

Figure 3. Cross Point Switch Diagram

In a typical point-to-point switching application users must configure the following for each channel:

1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Cross point enable bit (ch reg 0x96)
5. Perform a CDR reset and reset release (ch reg 0x0A)

Note, when using the cross point switch the local and multi-drive buffer should both be enabled regardless of the desired configuration.

The cross point switch can also be used to replicate data or perform a broadcast function. The options for this type of configuration include:

• 1:2 – any channel input to any 2 channels output
• 1:3 – any channel input to any 3 channels output
• 1:4 – any channel input to all 4 channels output

When the cross point switch is configured to replicate/broadcast data a master must be assigned during the cross point configuration. The master channel will have control over the CTLE adaption. All of the slave channels will be able to adapt their own DFE, but will not have control to adapt the CTLE. In this type of configuration there must be 1 channel assigned as a master. All other channels in the broadcast network must be assigned as slaves. There cannot be more than one master channel in a broadcast network. In a broadcast configuration, the straight through path connecting the broadcasting input to its own output needs to be enabled and set to have master control.

In a typical data replication/broadcast application users must configure the following for each channel:

1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Master/Slave assignment (ch reg 0x96) -- master/slave bit set to master, master function assigned by mux setting
5. Cross point enable bit (ch reg 0x96)
6. Perform a CDR reset and reset release (ch reg 0x0A)

7.3.5 DFE with VGA

A 5-tap DFE with a VGA can be enabled within the data path of each channel to assist with reducing the effects of cross talk, reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the selected adapt mode. Once the DFE has been enabled it can be configured to adapt only during lock acquisition or to adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights. However, when the DFE is configured manually the DFE auto-adaption should be disabled.

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity bit.

The VGA is located within the DFE block. The VGA has 2-bit control and allows for 3 levels of boost. The VGA can be used to assist in the recovery of extremely small signals. Note that the default VGA should be used for most applications.

7.3.6 Clock and Data Recovery

The CDR block consists of a Phase Locked Loop (PLL), reference clock based PPM counter, Input and Output Data Multiplexers (mux) and circuits to monitor single bit transitions and detect false locking. The CDR sampling position is fixed at the 0.5UI location for each bit.

By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output to the FIR filter and differential driver. Users can configure the CDR data to route the recovered clock and data to the PRBS checker. Users also have the option of configuring the output of the CDR to send raw non-retimed data, or data from the pattern generator.

The CDR requires the following in order to be properly configured:

• Input reference clock with proper reference clock divider setting to run the PPM counter.
• Expected data rates must be programmed into the CDR either through the rate/sub-rate Table 18 or entered manually with the corrected divider settings.

7.3.7 Reference Clock

The reference clock is not part of the CDR’s PLL. The reference clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed values in the rate/sub-rate Table 18 or the manually entered data rates.

The reference clock can be set to any of the 3 allowable frequencies independent of the data rate of the high speed channel. The input reference clock can be single-ended or differential for the 25 MHz or 125 MHz settings. If the 312.5 MHz setting is used, the input signaling type should be differential. The reference clock can be output through the CLK_MON pins for observation or daisy chaining the reference clock to the next device. If the CLK_MON port is used for daisy chaining then the output frequency should be set to 25 MHz.

If the reference clock port is configured to operate in single-ended mode, the 2.5V LVCMOS clock signal should be applied to the REF_CLK_P pin. In this configuration the REF_CLK_N pin should be floated (N/C). In this case the LVCMOS clock signal should be DC coupled into the REF_CLK_P pin. If the reference clock port is configured for differential mode, it is recommended to AC couple the clock signal into the DS125DF1610 device.

Configuring the reference clock frequency is done in share register 0x02[6:5]. Configuring the reference clock input port for single-ended or differential mode operation is done in share register 0x0B[4]. Enabling or disabling the CLK_MON port is done in share reg 0x0A[0]. Selecting the CLK_MON outputs to transmit the divided (25 MHz) or undivided (input frequency) clock frequency is done in share register 0x04[7].

7.3.8 Differential Driver with FIR Filter

The DS125DF1610 uses a 3-tap FIR filter to assist with transmit equalization. The FIR filter consists of a pre cursor tap, a main cursor tap and a post cursor tap. Each tap has a polarity bit and 64 available levels. By default, the main cursor tap is set to a positive polarity, while the pre cursor and post cursor taps are set to a negative polarity. Users can invert the polarity of all 3 FIR taps to invert the polarity of the output data.

The DS125DF1610 output driver can be manually powered off through SMBus register control.

7.3.9 Setting the Output V_OD

The output differential voltage (V_OD) of the driver is controlled by manipulating the drv_sel_vod bits, DEM bits, and FIR main cursor tap. The Table 6 below shows various settings for V_OD settings ranging from 150mV_PP to 1200 mV_PP. Using the FIR, DEM and drv_sel_vod bits is the recommended method for configuring the output V_OD for the best signal integrity.

7.3.10 Output Driver Polarity Inversion

In some applications it may be necessary to invert the polarity of the data transmitted from the retimer. To invert the polarity of the data read back the FIR polarity settings for the pre, main and post cursor taps and then invert these bits.

7.3.11 Driver Output Rise/Fall Time

In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory compliance. In others, it can reduce the crosstalk in the system.

The DS125DF1610 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew rate of the output drivers into the load capacitance. Alternatively, the DS125DF1610 can be configured to operate with a slightly greater rise/fall time if desired. By default the DS125DF1610 is configured to use the fastest edge rate.

7.3.12 Debug Features

7.3.12.3 Eye Opening Monitor

The DS125DF1610’s Eye Opening Monitor (EOM) measures the internal data eye at the input of the CDR and can be used for 2 functions:

1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement
2. Full Eye Diagram Capture

The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

• HEO [UI] = ch reg 0x27 ÷ 64
• VEO [mV] = ch reg 0x28 x 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a 64 x 64 array, where each cell in the matrix consists of an 16-bit word. Users can manually adjust the vertical scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the state machine and is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out 4 16-bit words of junk data that should be discarded followed by 4096 16-bit words that make up the 64 x 64 eye plot. The first actual word of the eye plot from the retimer is for (X, Y) position (0,0). Each time the eye plot data is read out the voltage position is incremented. Once the voltage position has incremented to position 63, the next read will cause the voltage position to reset to 0 and the phase position to increment. This process will continue until the entire 64 x 64 matrix is read out. Figure 4 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output data.

Figure 4. EOM Full Eye Capture Readout

To manually control the EOM vertical range, remove scaling control from the state machine then select the desired range:

1. Channel Reg 0x2C[6] → 0
2. See Table 8

Table 8. Eye Opening Monitor Vertical Range Settings

CH REG 0x11[7:6] VALUE	EOM VERTICAL RANGE [mV]
2’b00	±100
2'b01	±200
2'b10	±300
2'b11	±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

• Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
• Or single byte reads. With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this mode, the device must be addressed each time a new byte is read.

To perform a full eye capture with the EOM, follow these steps within the desired channel register set:

Table 9. Eye Opening Monitor Full Eye Capture Instructions

STEP	REGISTER [bits]	VALUE	DESCRIPTION
1	0x67[5]	0	Disable lock EOM lock monitoring
2	0x2C[6] 0x11[7:6]	0 2'b--	Set the desired EOM vertical range
3	0x11[5]	0	Power on the EOM
4	0x24[7]	1	Enable fast EOM
5	0x24[0] 0x25 0x26	1	Begin read out of the 64 x 64 array, discard first 4 words Ch reg 0x24[0] is self clearing. 0x25 is the MSB of the 16-bit word 0x26 is the LSB of the 16-bit word
6	0x25 0x26		Continue reading information until the 64 x 64 array is complete.
7	0x67[5] 0x2C[6] 0x11[5] 0x24[7,1]	1 1 1 0	Return the EOM to its original state. Undo steps 1-4

7.3.13 Interrupt Signals

The DS125DF1610 can be configured to report different events as interrupt signals. These interrupt signals do not impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits in the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The DS125DF1610 will report the occurrence of an interrupt through the INTERR_IO pin. The INTERR_IO pin is an open drain output that will pull the line low when an interrupt signal is triggered.

Note that all available interrupts are disabled by default. Users must activate the various interrupts before they can be used.

The interrupts available in the DS125DF1610 are:

• CDR loss of lock
• CDR locked
• Signal detect loss
• Signal detected
• PRBS pattern checker bit error detected
• HEO/VEO threshold violation

When an interrupt occurs, share register 0x08 and 0x09 report which channel generated the interrupt request. Users can then select the channel(s) that generated the interrupt request and service the interrupt by reading the appropriate interrupt status bits in the corresponding channel registers.

7.3.14 Other Features

7.4.1 SMBus Master Mode

SMBus master mode allows the DS125DF1610 to program itself by reading directly from an external EEPROM. When using the SMBus master mode, the DS125DF1610 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific guidelines:

• Maximum EEPROM size is 2048 Bytes
• Minimum EEPROM size for a single DS125DF1610 with individual channel configuration is 1417 Bytes (3 base header bytes + 3 address map bytes + 16 x 88 channel register bytes + 3 share register bytes; bytes are defined to be 8-bits)
• Set ENSMB = VDD through 1kΩ resistor, enable SMBus master mode
• The external EEPROM device address byte must be 0xA0
• The external EEPROM device must support 400kHz operation at 2.5V supply
• Set the SMBus address of the DS125DF1610 by configuring the ADDR0 and ADDR1 terminals.

When loading multiple DS125DF1610 devices from the same EEPROM, use these guidelines to configure the devices:

• Configure the SMBus addresses for each DS125DF1610 to be sequential. The first device in the sequence must have an address of 0x30.
• Daisy chain READEN and ALL_DONE from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time.
• All DS125DF1610 devices sharing the same EEPROM must be configured with the common channel bit set to 1. With common channel configuration enabled, each DS125DF1610 device will configure all 16 channels with the same settings.

When loading a single DS125DF1610 from an EEPROM, use these guidelines to configure the device:

• Set the common channel bit to 0 to allow for individual channel configuration. Or set the common channel bit to 1 to load the same configuration settings to all channels.
• When configuring individual channels, a 2048 Byte EEPROM must be used.
• If there are multiple DS125DF1610 devices on a PCB that require individual channel configuration, then each device must have its own EEPROM.

7.4.2 SMBus Slave Mode

7.4.3 Device Configuration in SMBus Slave Mode

The configurable settings of the DS125DF1610 may be set independently for each channel at any time after power up using the SMBus. A register write is accomplished when the controller sends a START condition on the SMBus followed by the Write address of the DS125DF1610 to be configured. After sending the Write address of the DS125DF1610, the controller sends the register address byte followed by the register data byte. The DS125DF1610 acknowledges each byte written to the controller according to the data link protocol of the SMBus Version 2.0 Specification. See this specification for additional information on the operation of the SMBus.

There are 3 types of device registers in the DS125DF1610. These are the global registers, shared registers and the channel registers. The global registers are programmed to access the various channel registers or the shared registers. The shared registers control or allow observation of settings which affect the operation of all channels of the DS125DF1610 at the greater device level.

The channel registers are used to set all the configuration settings of the DS125DF1610. They provide independent control for each channel of the DS125DF1610 for all the settable device characteristics. Any registers not described in the tables that follow should be treated as reserved. The user should not try to write new values to these registers. The user-accessible registers described in the tables that follow provide a complete capability for customizing the operation of the DS125DF1610 on a channel-by-channel basis.

7.5.1 Bit Fields in the Register Set

Many of the registers in the DS125DF1610 are divided into bit fields. This allows a single register to serve multiple purposes, which may be unrelated. Often configuring the DS125DF1610 requires writing a bit field that makes up only part of a register value while leaving the remainder of the register value unchanged.

The procedure for accomplishing this is to read in the current value of the register to be written, modify only the desired bits in this value, and write the modified value back to the register. Of course, if the entire register is to be changed, rather than just a bit field within the register, it is not necessary to read in the current value of the register first. In all the register configuration procedures described in the following sections, this procedure should be kept in mind. In some cases, the entire register is to be modified. When only a part of the register is to be changed, however, the procedure described above should be used.

Most register bits can be read or written to. However, some register bits are constrained to specific interface instructions. Register bits can have the following interface constraints:

• R - Read only
• RW - Read/Write
• RWSC - Read/Write, self clearing
• W - Write only

7.5.2 Writing to and Reading from the Global/Shared/Channel Registers

Global registers can be accessed from the shared register page and also the channel register pages. There are three global registers in the DS125DF1610:

1. Register 0xFC
2. Register 0xFD
3. Register 0xFF

Registers 0xFC and 0xFD are used to select the channel registers to be written to. To select a channel write a 1 to its corresponding bit in these global registers. Note more than one channel may be written to by setting multiple bits in registers 0xFC and 0xFD. However, when performing an SMBus read transaction only one channel can be selected at a time. If multiple channels are selected when attempting to perform an SMBus read, the device will return 0x00.

Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read-modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a single channel in the 0xFC or 0xFD registers. This type of configuration allows for the reading of a single channel's register information and then writing to all channels with the modified value.

Table 12. Shared-Channel Select Global Register

Table 13. Shared Registers

Table 14. Channel Registers, 0 to 1F

Table 15. Channel Registers, 20 to 39

Table 16. Channel Registers, 3A to 59

Table 17. Channel Registers, 5A to 9B