ZHCSCD5B April   2014  – January 2017 DS125DF1610

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Additional Thermal Information
    6. 6.6 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Data Path Operation
      2. 7.3.2  AC-Coupled Receiver with Signal Detect
      3. 7.3.3  CTLE
      4. 7.3.4  Cross Point Switch
      5. 7.3.5  DFE with VGA
      6. 7.3.6  Clock and Data Recovery
      7. 7.3.7  Reference Clock
      8. 7.3.8  Differential Driver with FIR Filter
      9. 7.3.9  Setting the Output VOD
      10. 7.3.10 Output Driver Polarity Inversion
      11. 7.3.11 Driver Output Rise/Fall Time
      12. 7.3.12 Debug Features
        1. 7.3.12.1 Pattern Generator
        2. 7.3.12.2 Pattern Checker
        3. 7.3.12.3 Eye Opening Monitor
      13. 7.3.13 Interrupt Signals
      14. 7.3.14 Other Features
        1. 7.3.14.1 Lock Sequencer
        2. 7.3.14.2 RESET_IO Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode
      2. 7.4.2 SMBus Slave Mode
        1. 7.4.2.1 SDA and SDC
        2. 7.4.2.2 SMBus Address Configuration
      3. 7.4.3 Device Configuration in SMBus Slave Mode
    5. 7.5 Programming
      1. 7.5.1 Bit Fields in the Register Set
      2. 7.5.2 Writing to and Reading from the Global/Shared/Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Typical Application Performance Plots
    3. 8.3 Initialization Setup
      1. 8.3.1 Data Rate Selection (Rate/Sub-Rate Table)
      2. 8.3.2 Data Rate Selection (Manual Programming)
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Filtering
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage (VDD) –0.5 2.75 V
LVCMOS Input/Output Voltage –0.5 2.75 V
Open Drain I/O Supply Voltage –0.5 4.0 V
CML Input Voltage –0.5 (VDD + 0.5) V
CML Input Current –30 30 mA
Storage temperature range, Tstg -40 150 °C
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications

6.2 Handling Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4,000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1,000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply Voltage 2.375 2.5 2.625 V
Ambient Temperature –40 25 85 °C
SMBus (SDA, SCL), INTERR_IO 2.5 3.6 V
Maximum Continuous Junction Temperature while Device is Operational 115 °C

6.4 Thermal Information

THERMAL METRIC(1) (2) DS125DF1610
FCBGA ABB
(196) PINS		 UNIT
RθJA Junction-to-ambient thermal resistance 18.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.7
RθJB Junction-to-board thermal resistance 5.3
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 5.3
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Thermal model available upon request

6.5 Additional Thermal Information

BOARD θJC (°C / W) θJA (°C / W) ψJT(°C / W) ψJB(°C / W)
JEDEC 4 layer board, no airflow 0.7 18.2 0.8 5.3
8x6 inches 10 layer, no airflow 0.7 7.2 0.3 3.2
8x6 inches 20 layer, no airflow 0.7 6.4 0.3 3.2
8x6 inches 30 layer, no airflow 0.7 6.3 0.3 3.2

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
R_baud Input Data Rate Full Rate 9.8 12.5 Gbps
Half Rate 4.9 6.25 Gbps
Quarter Rate 2.45 3.125 Gbps
Eighth Rate 1.225 1.5625 Gbps
POWER SUPPLY
W Power Consumption per Active Channel CTLE only, 800mVp-p VOD, per channel,
CDR locked		 175 mW
CDR Locking with CTLE only, 800mVp-p VOD,
per channel		 325 mW
CTLE and DFE, 800mVp-p VOD, per channel,
CDR locked		 200 323 mW
CDR Locking with CTLE and DFE, 800mVp-p VOD 350 535.5 mW
PRBS Checker 100 mW
PRBS Generator 105 mW
WSTATIC Device Static Power Consumption Power Applied to Device,
No Signals Present		 325 1325 mW
NTPS Power Supply Noise Tolerance 50 Hz to 100 Hz 100 mVPP
100 Hz to 10 MHz 40
10 MHz to 5.0 GHz 10
LVCMOS
V IH High level input voltage 1.75 VDD V
VIL Low level input voltage GND 0.7 V
VOH High level output voltage IOH = 4mA 2 V
VOL Low level output voltage IOL = -4mA 0.4 V
IIH Input High Leakage current Vinput = VDD,
Open Drain terminals		 30 µA
Vinput = VDD,
JTAG terminals, Ref_CLK terminals		 25 µA
Vinput = VDD,
ADDR, READ_EN, ALL_DONE terminals,
EN_SMB terminal		 75 µA
IIL Input Low Leakage current Vinput = 0V,
Open drain terminals		 -15 µA
Vinput = 0V,
JTAG terminals, Ref_CLK terminals		 -45 µA
Vinput = 0V,
ADDR, READ_EN, ALL_DONE terminals,
EN_SMB terminal		 -120 µA
RX INPUTS
RRD DC Input Resistance 80 100 120 Ω
VRX-IN Input Differential Voltage Differential voltage seen at the high speed input terminals (2) 1600 mVPP
VSDAT Signal Detect Assert Threshold Default setting
1T pattern, 12.5 Gbps		 110 mVPP
Default setting
PRBS-31, 12.5 Gbps		 24
VSDDT Signal Detect De-Assert Threshold Default setting
1T pattern, 12.5 Gbps		 70 mVPP
Default setting
PRBS-31, 12.5 Gbps		 21
Vcm-RX Input common mode Internal coupling cap VRX-IN / 4 VDD - (VRX-IN/ 4) V
TX OUTPUTS
VOD Output Differential Voltage drv_sel_vod[5:0] = 31, DEM, FIR = default 725 935 1135 mVPP
drv_sel_vod[5:0] = 15, DEM, FIR = default 350 470 595
ΔVOD Step Size for drv_sel_vod Control Default DEM, and FIR settings 50 mVPP
ΔVODVT Change in Output Differential Voltage due to Change in Temperature and Voltage <15 mVPP
TRd Output Differential Resistance 100 Ω
tr, tf Output Rise/Fall Time 20% - 80% using 8T Pattern, fir_sel_edge = default 35 ps
IOS Output Short Circuit Current Differential Driver Output Pin Short to GND -16 mA
RETIMER JITTER SPECS
JTJ Total Output Jitter PRBS-15 pattern, measured to 1e-12
10.3125 Gbps		 0.08 UI
JRJ Output Random Jitter PRBS-15 pattern, measured to 1e-12
10.3125 Gbps		 3.6 mUIRMS
JDJ Output Deterministic Jitter PRBS-15
10.3125 Gbps		 0.03 UI
JPEAK Jitter Peaking Data Rate = 9.8 Gbps,
Peaking Frequency =
1 - 3 MHz		 <1 dB
Data Rate = 12.5 Gbps
Peaking Frequency =
3 - 8 MHz		 <1
BWPLL PLL Bandwidth at -3 dB Data Rate = 9.8 Gbps 5 MHz
Data Rate = 12.5 Gbps 10
JTOL Input Jitter Tolerance Jitter per SFF-8431 Appendix D.11 Combination of DJ PJ and RJ >0.7 UI
RETIMER TIMING SPECS
tD Propagation Delay from Rx inputs to Tx outputs No Cross Point 3UI + 220ps ps
Cross Point enabled 3UI + 230ps
tSK Channel To Channel Skew <80 ps
RECOMMENDED REFERENCE CLOCK SPECS
REFf Input Reference Clock Frequency 25 MHz
125
312.5
REFPPM Reference Clock PPM Tolerance REFf = 25 MHz(1) -100 100 PPM
REFIDC Input Reference Clock Duty Cycle REFf = 25 MHz(1) 40% 50% 60%
REFODC Intrinsic Reference Clock Duty Cycle Distortion Intrinsic Duty Cycle Distortion of the reference clock output from the CLK_MON pins ±1%
REFVID Reference Clock Input Differential Voltage Differential mode(1) 200 1200 mVPP
REFVIH Reference Clock Signle-Ended Input High Threshold Single-ended mode.
Signal DC coupled to REF_CLK_P,
REF_CLK_N is float		 1.75 V
REFVIL Reference Clock Single-Ended Input Low Threshold Single-ended mode.
Signal DC coupled to REF_CLK_P,
REF_CLK_N is float		 0.7 V
SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)
VIH Input High Level Voltage SDA and SCL 1.75 3.6 V
VIL Input Low Level Voltage SDA and SCL GND 0.8 V
CIN Input Pin Capacitance <5 pF
VOL Low Level Output Voltage SDA or SCL
IOL = 1.25 mA		 0.4 V
IIN Input Current SDA or SCL, VINPUT = VIN, VDD, GND -15 15 µA
TR SDA Rise Time Read Operation SDA, pullup resistor = 1 kΩ, Cb = 50pF 150 ns
TF SDA Fall Time Read Operation SDA, pullup resistor = 1 kΩ, Cb = 50pF 4.5 ns
RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SLAVE MODE)
fSCL SCL Clock Frequency 10 100 400 kHz
tHD:DAT Data Hold Time 0.75 ns
tSU:DAT Data Setup Time 100 ns
RECOMMENDED SMBus SWITCHING CHARACTERISTICS (MASTER MODE)
FSCL SCL Clock Frequency 400 kHz
TLOW SCL Low Period 1.25 µs
THIGH SCL High Period 1.25 µs
THD:STA Hold Time Start Operation 0.6 µs
TSU:STA Setup Time Start Operation 0.6 µs
THD:DAT Data Hold Time 0.9 µs
TSD:DAT Data Setup Time 0.1 µs
TSU:STO Stop Condition Setup Time 0.6 µs
TBUF Bus Free Time between Stop-Start 1.3 µs
TR SCL and SDA Rise Time 300 ns
TF SCL and SDA Fall Time 300 ns
RECOMMENDED JTAG SWITCHING CHARACTERISTICS
tTCK TCK Clock Period 100 ns
tSU TDI, TMI Setup Time to TCK 50 ns
tHD TDI, TMS Hold Time to TCK 50 ns
tDLY TCK Falling Edge to TDO 50 ns
(1) Parameter is specified by design and not tested at final production
(2) Parameter is not tested at final production