ZHCSCD5B April   2014  – January 2017 DS125DF1610

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Additional Thermal Information
    6. 6.6 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Data Path Operation
      2. 7.3.2  AC-Coupled Receiver with Signal Detect
      3. 7.3.3  CTLE
      4. 7.3.4  Cross Point Switch
      5. 7.3.5  DFE with VGA
      6. 7.3.6  Clock and Data Recovery
      7. 7.3.7  Reference Clock
      8. 7.3.8  Differential Driver with FIR Filter
      9. 7.3.9  Setting the Output VOD
      10. 7.3.10 Output Driver Polarity Inversion
      11. 7.3.11 Driver Output Rise/Fall Time
      12. 7.3.12 Debug Features
        1. 7.3.12.1 Pattern Generator
        2. 7.3.12.2 Pattern Checker
        3. 7.3.12.3 Eye Opening Monitor
      13. 7.3.13 Interrupt Signals
      14. 7.3.14 Other Features
        1. 7.3.14.1 Lock Sequencer
        2. 7.3.14.2 RESET_IO Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode
      2. 7.4.2 SMBus Slave Mode
        1. 7.4.2.1 SDA and SDC
        2. 7.4.2.2 SMBus Address Configuration
      3. 7.4.3 Device Configuration in SMBus Slave Mode
    5. 7.5 Programming
      1. 7.5.1 Bit Fields in the Register Set
      2. 7.5.2 Writing to and Reading from the Global/Shared/Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Typical Application Performance Plots
    3. 8.3 Initialization Setup
      1. 8.3.1 Data Rate Selection (Rate/Sub-Rate Table)
      2. 8.3.2 Data Rate Selection (Manual Programming)
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Filtering
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

The high speed inputs and outputs have been optimized to work with interconnects using a controlled differential impedance of 100Ω. Vias should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board.

10.2 Layout Example

Common BGA routing techniques such as trace necking, using blind vias and buried vias, are OK as long as the differential traces are balanced in their routing and the signals see few impedance changes. For example, necking lengths should be the same for the differential traces and implemented symmetrically for both traces. Figure 10 shows general Dos and Don'ts for high speed layout, such as differential trace gathering, differential trace necking, and high speed signal and return via implementation.

DS125DF1610 LayoutGuidelines.gif Figure 10. Layout Guidelines