DLPS292A July   2025  – December 2025 DLPC8424 , DLPC8444 , DLPC8454

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Compatability Table
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1  Initialization, Board Level Test, and Debug
    3. 5.2  V-by-One Interface Input Data and Control
    4. 5.3  FPD-Link Port(s) Input Data and Control
    5. 5.4  DSI Input Data and Clock (Not Supported in DLPC8424, DLPC8444, and DLPC8454)
    6. 5.5  DMD SubLVDS Interface
    7. 5.6  DMD Reset and Low Speed Interfaces
    8. 5.7  Flash Interface
    9. 5.8  Peripheral Interfaces
    10. 5.9  GPIO Peripheral Interface
    11. 5.10 Clock and PLL Support
    12. 5.11 Power and Ground
    13. 5.12 I/O Type Subscript Definition
    14. 5.13 Internal Pullup and Pulldown Characteristics
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2.     23
    3. 6.2  ESD Ratings
    4. 6.3  Recommended Operating Conditions
    5. 6.4  Thermal Information
    6. 6.5  Power Electrical Characteristics
    7. 6.6  Pin Electrical Characteristics
    8. 6.7  DMD SubLVDS Interface Electrical Characteristics
    9.     30
    10. 6.8  DMD Low Speed Interface Electrical Characteristics
    11.     32
    12. 6.9  V-by-One Interface Electrical Characteristics
    13. 6.10 FPD Link LVDS Electrical Characteristics
    14. 6.11 USB Electrical Characteristics
    15.     36
    16. 6.12 System Oscillator Timing Requirements
    17.     38
    18. 6.13 Power Supply and Reset Timing Requirements
    19.     40
    20. 6.14 V-by-One Interface General Timing Requirements
    21.     42
    22. 6.15 FPD Link Interface General Timing Requirements
    23. 6.16 Flash Interface Timing Requirements
    24.     45
    25. 6.17 Source Frame Timing Requirements
    26.     47
    27. 6.18 Synchronous Serial Port Interface Timing Requirements
    28.     49
    29. 6.19 I2C Interface Timing Requirements
    30. 6.20 Programmable Output Clock Timing Requirements
    31. 6.21 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    32.     53
    33. 6.22 DMD Low Speed Interface Timing Requirements
    34.     55
    35. 6.23 DMD SubLVDS Interface Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 V-by-One Interface
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 DMD (SubLVDS) Interface
      5. 7.3.5 Serial Flash Interface
      6. 7.3.6 GPIO Supported Functionality
        1.       67
        2.       68
      7. 7.3.7 Debug Support
  9. 8 Power Supply Recommendations
    1. 8.1 System Power-Up and Power-Down Sequence
    2. 8.2 DMD Fast Park Control (PARKZ)
    3. 8.3 Power Supply Management
    4. 8.4 Hotplug Usage
    5. 8.5 Power Supplies for Unused Input Source Interfaces
    6. 8.6 Power Supplies
      1. 8.6.1 Power Supplies DLPA3085 or DLPA3082
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout Guideline for DLPC8424 or DLPC8444 or DLPC8454 Reference Clock
        1. 9.1.1.1 Recommended Crystal Oscillator Configuration
      2. 9.1.2 V-by-One Interface Layout Considerations
      3. 9.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 9.1.4 Power Supply Layout Guidelines
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Device Nomenclature
      1. 10.5.1 Device Markings
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
      1. 10.8.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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5.1 Initialization, Board Level Test, and Debug

PIN I/O (1) DESCRIPTION
NAME NO.
PROJ_ON AP2 I1 Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal causes the Controller to PARK the DMD, but does not power down the DMD (the DLPA does that instead). The minimum high time is 200 ms. The minimum low time is 200 ms.
RESETZ P2 I1 Power-on reset (active low input with a hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All controller power and clocks must be stable before this reset is de-asserted. No signals are in the active state while RESETZ is asserted. This pin is typically connected to the RESETZ pin of the DLPA PMIC.
PARKZ AR1 I1 DMD fast park control (active low Input with a hysteresis buffer). This signal is used to quickly park the DMD when loss of power is imminent. The longest lifetime of the DMD can not be achieved with the fast park operation; therefore, this signal is intended to only be asserted when a normal park operation is unable to be completed. The PARKZ signal is typically provided from the DLPA interrupt output signal.
JTAGTCK V24 I2 JTAG and ARM-ICE Serial Data Clock. This signal is shared between JTAG and ARM-ICE (TI test only), operation. Includes a weak internal pulldown.
JTAGTMS1 U23 I2 JTAG Test Mode Select. Includes a weak internal pullup.
JTAGTMS2 W25 I2 ARM-ICE Test Mode Select For normal operation, this pin must be left open or unconnected. Includes a weak internal pullup.
JTAGTRSTZ AA25 I2 JTAG, ARM-ICE Reset.
For normal operation, this pin must be pulled to ground through an external resistor with value 8 kΩ or less. Failure to pull this pin low during normal operation causes start-up and initialization problems.
For JTAG Boundary Scan and ARM-ICE Debug operation, this pin must be pulled-up or left disconnected. Includes a weak internal pullup and Hysteresis.
JTAGTDI Y24 I2 JTAG, ARM-ICE, and CPU MBIST: Serial Data In. Includes weak internal pullup.
JTAGTDO1 V22 B14 JTAG Serial Data Out.
JTAGTDO2 W23 B14 ARM-ICE Serial Data Out. For normal operation, this pin requires an external pullup resistor with a value of ≤ 9.15 kΩ.
ETM_TRACECLK U25 O14 Reserved Pin, must be left unconnected.
ETM_TRACECTL T24 O14 Reserved Pin, must be left unconnected.
TSTPT_0 T22 B14 Test pin 0
This pin has an internal pulldown and require an external pullup resistor (no pullup: Normal Boot, pullup: Wait for Host commands) with a value of ≤ 9.15 kΩ.
TSTPT_1 R25 B14 Test pin 1
This pin has an internal pulldown for Normal Boot operation.
TSTPT_2 R23 B14 Test pin 2
This pin has an internal pulldown and require an external pullup resistor (no pullup: I2C address = 0x36, pullup: I2C address = 0x34) with a value of ≤ 9.15 kΩ.
TSTPT_3 P24 B14 Test pin 3
This pin has an internal pulldown and require an external pullup resistor (no pullup: Host interface is USB or I2C, pullup: Host interface is I2C only) with a value of ≤ 9.15 kΩ.
TSTPT_4 N25 B14 Test pin 4
This pin has an internal pulldown resistor.
TSTPT_5 P22 B14 Test pin 5
This pin has an internal pulldown resistor.
TSTPT_6 N23 B14 Test pin 6
This pin has an internal pulldown resistor.
TSTPT_7 M24 B14 Test pin 7
This pin has an internal pulldown resistor.
GPTP0 AA23 B13 General Purpose Test pin 0
This pin has an internal pulldown and require an external pullup resistor (no pullup: external crystal, pullup: external clock) with a value of ≤ 9.15 kΩ.
GPTP1 AB22 B13 General Purpose Test pin 1
This pin has an internal pulldown resistor.
GPTP2 AC25 B13 General Purpose Test pin 2
This pin has an internal pulldown resistor.
ATB_0_H AH4 PWR Reserved Pin, must be left unconnected.
ATB_1_H AJ5 PWR Reserved Pin, must be left unconnected.
ATEST G13 PWR Reserved Pin, must be left unconnected.
CAP_VDDS_FLSH AD22 PWR External bias capacitance.
CAP_VDDS_INTF AJ21 PWR External bias capacitance.
IFORCE L3 PWR Manufacturing use only. Must be tied to ground.
VSENSE K2 PWR Reserved Pin, must be left unconnected.
HWTEST_EN Y22 I2 Reserved Pin.
This signal must be connected directly to ground on the PCB for normal operation. Includes weak internal pulldown and hysteresis.
(1) See Section 5.12 for more information on I/O definitions