ZHCSLG8E August   2020  – August 2024 DLPC230S-Q1 , DLPC231S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000S-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000S-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23xS-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23xS-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方产品免责声明
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 静电放电警告
    4. 9.4 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
  • ZDQ|324
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.18 Flash Interface Timing Requirements

The DLPC23xS-Q1 ASIC flash memory interface consists of an SPI serial interface. See Section 7.3.4.
(1)MINMAXUNIT
fclockClock frequency, FLSH_SPI_CLKWhen VCC3IO_FLSH = 3.3VDC9.99850.01(2)MHz
tp_clkperClock period, FLSH_SPI_CLK
(50% reference points)		When VCC3IO_FLSH = 3.3VDC20.0100ns
tp_whPulse duration low, FLSH_SPI_CLK
(50% reference points)		When VCC3IO_FLSH = 3.3VDC9ns
tp_wlPulse duration high, FLSH_SPI_CLK
(50% reference points)		When VCC3IO_FLSH = 3.3VDC9ns
ttTransition time – all input signals20% to 80% reference points6ns
tp_suSetup time – FLSH_SPI_DIO[3:0] valid before FLSH_SPI_CLK falling edge
(50% reference points)		When VCC3IO_FLSH = 3.3VDC7.0ns
tp_hHold time – FLSH_SPI_DIO[3:0] valid after FLSH_SPI_CLK falling edge50% reference points0.0ns
tp_clqvFLSH_SPI_DIO[3:0] output delay valid time

(with respect to falling edge of FLSH_SPI_CLK or falling edge of FLSH_SPI_CSZ)
(50% reference points)

When VCC3IO_FLSH = 3.3VDC–3.03.0ns
(1) The DLPC23xS-Q1 communicates with flash devices using a slight variant of SPI Transfer Mode 0 (that is, clock polarity = 0, clock phase = 0). Instead of capturing MISO data on the clock edge opposite from that used to transmit MOSI data, the DLPC23xS-Q1 captures MISO data on the same clock edge used to transmit the next MOSI data. As such, the DLPC23xS-Q1 Flash SPI interface requires that MISO data from the flash device remain active until the end of the full clock cycle to allow the last data bit to be captured. This is shown in Figure 5-8.
(2) The actual maximum clock rate driven from the DLPC23xS-Q1 can be slightly less than this value.
DLPC230S-Q1 DLPC231S-Q1 Flash Interface TimingFigure 5-7 Flash Interface Timing
DLPC230S-Q1 DLPC231S-Q1 Flash Interface Data Capture RequirementsFigure 5-8 Flash Interface Data Capture Requirements