ZHCSHX7B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZXS|216
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.5 Memory Interface

PINI/OI/OCLOCK
NAMENO.POWERTYPESYSTEMDESCRIPTION
MEM_CLKF21.80 VOsN/ADDR memory, Differential Memory Clock.
MEM_CLKZF1
MEM_A0H1OsMEM_CLKDDR memory, Multiplexed Row and Column Address.
MEM_A1C1
MEM_A2F4
MEM_A3D2
MEM_A4H2
MEM_A5G1
MEM_A6G2
MEM_A7G3
MEM_A8F3
MEM_A9E1
MEM_A10B1
MEM_A11D1
MEM_A12E2
MEM_BA0J1OsMEM_CLKDDR memory, Bank Select.
MEM_BA1J2
MEM_RASZD3OsMEM_CLKDDR memory, Row Address Strobe  (Active low).
MEM_CASZJ3OsMEM_CLKDDR memory, Column Address Strobe  (Active low).
MEM_WEZC2OsMEM_CLKDDR memory, Write Enable (Active low).
MEM_CSZK2OsMEM_CLKDDR memory, Chip Select (Active low).
MEM_CKEK1OsMEM_CLKDDR memory, Clock Enable (Active high).
MEM_ODTE4OsMEM_CLKDDR memory, On die termination (ODT).  ODT is not verified and supported operational mode. This pin should be left open or connected to corresponding DDR2 pin.
MEM_RSTC3OsMEM_CLKDDR memory, Reset.  Do Not connect.
MEM_ZQJ4OsMEM_CLKDDR memory, External pad where to connect the external impedance calibration resistor.  The user connects the PAD pin through an external 240 Ω ± 1% resistor to ground.
MEM_DQS0N1BSDN/ADDR memory, Lower Byte, R/W Data Strobe.
MEM_DQSZ0N2BSDN/ADDR memory, Lower Byte, R/W Data Strobe, inverted.
MEM_DQ0P2BsMEM_DQS0DDR memory, Lower Byte, Bidirectional R/W Data.
MEM_DQ1R1
MEM_DQ2P1
MEM_DQ3M2
MEM_DQ4L3
MEM_DQ5M1
MEM_DQ6L2
MEM_DQ7L1
MEM_DQS1R41.80 VBsN/ADDR memory, Upper Byte, R/W Data Strobe. 
MEM_DQSZ1T4BSDN/ADDR memory, Upper Byte, R/W Data Strobe, inverted.
MEM_DQ8T6BsMEM_DQS1DDR memory, Upper Byte, Bidirectional R/W Data.
MEM_DQ9R6
MEM_DQ10T5
MEM_DQ11R5
MEM_DQ12P5
MEM_DQ13T3
MEM_DQ14T2
MEM_DQ15R3