ZHCSE69E November   2014  – May 2025 DLP9500UV

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  LVDS Timing Requirements
    8. 6.8  LVDS Waveform Requirements
    9. 6.9  Serial Control Bus Timing Requirements
    10. 6.10 Systems Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DLPC410—Digital Controller for DLP Discovery 4100 Chipset
      2. 7.3.2 DLPA200 - DMD Micromirror Drivers
      3. 7.3.3 DLPR410—PROM for DLP Discovery 4100 Chipset
      4. 7.3.4 DLP9500—DLP 0.95 1080p 2xLVDS UV Type-A DMD 1080p DMD
        1. 7.3.4.1 DLP9500UV 1080p Chipset Interfaces
          1. 7.3.4.1.1 DLPC410 Interface Description
            1. 7.3.4.1.1.1 DLPC410 IO
            2. 7.3.4.1.1.2 Initialization
            3. 7.3.4.1.1.3 DMD Device Detection
            4. 7.3.4.1.1.4 Power Down
          2. 7.3.4.1.2 DLPC410 to DMD Interface
            1. 7.3.4.1.2.1 DLPC410 to DMD IO Description
            2. 7.3.4.1.2.2 Data Flow
          3. 7.3.4.1.3 DLPC410 to DLPA200 Interface
            1. 7.3.4.1.3.1 DLPA200 Operation
            2. 7.3.4.1.3.2 DLPC410 to DLPA200 IO Description
          4. 7.3.4.1.4 DLPA200 to DLP9500UV Interface
            1. 7.3.4.1.4.1 DLPA200 to DLP9500UV Interface Overview
      5. 7.3.5 Measurement Conditions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single Block Mode
      2. 7.4.2 Dual Block Mode
      3. 7.4.3 Quad Block Mode
      4. 7.4.4 Global Block Mode
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
      2. 7.5.2 Numerical Aperture and Stray Light Control
      3. 7.5.3 Pupil Match
      4. 7.5.4 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Package Thermal Resistance
      2. 7.6.2 Case Temperature
      3. 7.6.3 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On and Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DMD Reflectivity Characteristics
        1. 8.1.1.1 Design Considerations Influencing DMD Reflectivity
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Device Description
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Up Sequence (Handled by the DLPC410)
      2. 8.3.2 DMD Power-Up and Power-Down Procedures
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Impedance Requirements
        2. 8.4.1.2 PCB Signal Routing
        3. 8.4.1.3 Fiducials
        4. 8.4.1.4 PCB Layout Guidelines
          1. 8.4.1.4.1 DMD Interface
            1. 8.4.1.4.1.1 Trace Length Matching
          2. 8.4.1.4.2 DLP9500UV Decoupling
            1. 8.4.1.4.2.1 Decoupling Capacitors
          3. 8.4.1.4.3 VCC and VCC2
          4. 8.4.1.4.4 DMD Layout
          5. 8.4.1.4.5 DLPA200
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Device Marking
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MINNOMMAXUNIT
ELECTRICAL
VCCSupply voltage for LVCMOS core logic (2)(3)3.03.33.6V
VCCISupply voltage for LVDS receivers (2) (3)3.03.33.6V
VCC2Mirror electrode and HVCMOS supply voltage (2) (3)8.258.58.75V
VMBRSTClocking pulse waveform voltage applied to MBRST[15:0] input pins (supplied by DLPA200)–2726.5V
MECHANICAL
Static load applied to electrical interface area, see (4) Figure 6-51334N
Static load applied to the thermal interface area, see (5) Figure 6-5156N
Static load applied to Datum 'A' interface area Figure 6-5712N
ENVIRONMENTAL (6)
Illumination power density (4) (12)< 363nm (7)2mW/cm2
363 to 400nm(8)5.2W/cm2
12.5W
400 to 420nm(8)11W/cm2
26.6W
363 to 420nm total (8)(9)11W/cm2
26.6W
> 420nmThermally limited (8)W/cm2
TCCase/array temperature (10)(11)2030 (12)°C
TGRADIENTDevice temperature gradient – operational (13)10°C
RHRelative humidity (non-condensing)(14)95%RH
Operating landed duty cycle (15)25%
(1) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
(2) All voltages referenced to VSS (ground).
(3) Voltages VCC, VCC2, and VCCI, are required for proper DMD operation. VSS must also be connected.
(4) Load should be uniformly distributed across the entire electrical interface area.
(5) Load should be uniformly distributed across the thermal interface area. Refer to Figure 6-5.
(6) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.
(7) The maximum operating conditions for operating temperature and illumination power density for wavelengths < 363nm should not be implemented simultaneously.
(8) Also limited by the resulting micromirror array temperature. Refer to Case Temperature and Micromirror Array Temperature Calculation for information related to calculating the micromirror array temperature.
(9) The total integrated illumination power density from 363 to 420nm shall not exceed 11 W/cm2 (or 26.6 W evenly distributed on the active array area). Therefore if 2.5 W/cm2 of illumination is used in the 363 to 400nm range, then illumination in the 400 to 420nm range must be limited to 8.5 W/cm2 .
(10) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See Micromirror Array Temperature Calculation for further details.
(11) Temperature is the highest measured value of any test point shown in Figure 18 or the active array as calculated by the Micromirror Array Temperature Calculation.
(12) See the Micromirror Array Temperature Calculation for thermal test point locations, package thermal resistance, and device temperature calculation.
(13) As either measured, predicted, or both between any two points - measured on the exterior of the package, or as predicted at any point inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.
(14) Various application parameters can affect the optimal, long-term performance of the DMD, including illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, and power-on or power-off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle. Contact your local TI representative for additional information related to optimizing the DMD performance.
(15) Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the other state (–12° or 12°).