ZHCSR38A 数据表 | 德州仪器 TI.com.cn

ZHCSR38A November 2022 – September 2023 DLP801RE

PRODUCTION DATA

6.7 Timing Requirements

Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER DESCRIPTION		MIN	MAX	UNIT
SCP
t_{SCP_DS}	SCPDI clock setup time (before SCPCLK falling-edge)⁽¹⁾	800		ns
t_{SCP_DH}	SCPDI hold time (after SCPCLK falling-edge)⁽¹⁾	900		ns
t_{SCP_NEG_ENZ}	Time between falling edge of SCPENZ and the rising edge of SCPCLK⁽¹⁾	1		µs
t_{SCP_POS_ENZ}	Time between falling edge of SCPCLK and the rising edge of SCPENZ⁽¹⁾	1		µs
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tri-state).⁽¹⁾		960	ns
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high-level)	1		1/F_scpclk
t_r	Rise time (20% to 80%). See ⁽²⁾		200	ns
t_f	Fall time (80% to 20%). See ⁽²⁾		200	ns
LVDS
t_{R_LVDS}	Rise time (20% to 80%). See ⁽³⁾		500	ps
t_{F_LVDS}	Fall time (80% to 20%). See ⁽³⁾		500	ps
t_C	Clock Cycle Duration for DCLK_C and DCLK_D⁽⁴⁾	2.5		ns
t_W	Pulse Duration for DCLK_C/D⁽⁴⁾	1.19		ns
t_{SU_data}	Setup Time for High-speed data(15:0) before DCLK⁽⁴⁾	350		ps
t_{SU_sctrl}	Setup Time for SCTRL before DCLK⁽⁴⁾	330		ps
t_{H_data}	Hold time for High-speed data(15:0) after DCLK⁽⁴⁾	150		ps
t_{H_sctrl}	Hold Time for SCTRL after DCLK⁽⁴⁾	170		ps
t_{SKEW_C2D}	Skew tolerance between Channel C and Channel D⁽⁵⁾⁽⁶⁾⁽⁷⁾	–1.25	1.25	ns

(6) Channel C (Bus C) includes the following LVDS pairs: DCLK_C, SCTRL_C, and D_C

(7) Channel D (Bus D) includes the following LVDS pairs: DCLK_D, SCTRL_D, and D_D.