ZHCSR38A November   2022  – September 2023 DLP801RE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     12
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     16
    10. 6.8  System Mounting Interface Loads
    11.     18
    12. 6.9  Micromirror Array Physical Characteristics
    13.     20
    14. 6.10 Micromirror Array Optical Characteristics
    15.     22
    16. 6.11 Window Characteristics
    17. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Window Aperture Illumination Overfill Calculation
    9. 7.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  12. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Device Markings
    4. 11.4 Documentation Support
      1. 11.4.1 Related Documentation
    5. 11.5 接收文档更新通知
    6. 11.6 支持资源
    7. 11.7 Trademarks
    8. 11.8 静电放电警告
    9. 11.9 术语表
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

9.2 DMD Power Supply Power-Up Procedure

  • During power-up, VDD and VDDI must always start and settle before VCC2 is are applied to the DMD.
  • Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the requirements listed in Section 6.1 and in Section 6.4.
  • During power-up, LVCMOS input pins must not be driven high until after VDD and VDDI have settled at operating voltages listed in Section 6.4 table.