ZHCSMW9B October   2021  – April 2024 DLP800RE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Timing Requirements
    9.     15
    10. 5.8  System Mounting Interface Loads
    11.     17
    12. 5.9  Micromirror Array Physical Characteristics
    13.     19
    14. 5.10 Micromirror Array Optical Characteristics
    15.     21
    16. 5.11 Window Characteristics
    17. 5.12 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Requirements
    2. 8.2 DMD Power Supply Power-Up Procedure
    3. 8.3 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
        1. 9.2.3.1 Voltage Signals
  11. 10Device and Documentation Support
    1. 10.1 第三方产品免责声明
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
    3. 10.3 Device Markings
    4. 10.4 Documentation Support
      1. 10.4.1 Related Documentation
    5. 10.5 接收文档更新通知
    6. 10.6 支持资源
    7. 10.7 Trademarks
    8. 10.8 静电放电警告
    9. 10.9 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

9.2.1 Layers

The layer stack-up and copper weight for each layer is shown in Table 9-1. Small subplanes are allowed on signal routing layers to connect components to major subplanes on top and bottom layers if necessary.

Table 9-1 Layer Stack-Up
LAYER NO.LAYER NAMECOPPER WT. (oz.)COMMENTS
1Side A—DMD only1.5DMD, escapes, low frequency signals, power subplanes
2Ground1Solid ground plane (net GND)
3Signal0.550Ω and 100Ω differential signals
4Ground1Solid ground plane (net GND)
5VDD and VDDI1+1.8V power plane
6Signal0.550Ω and 100Ω differential signals
7Ground1Solid ground plane (net GND)
8Side B—All other Components1.5Discrete components, low frequency signals, power subplanes