ZHCSA87F August   2012  – June 2019 DLP7000

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Window Characteristics
    14. 7.14 Chipset Component Usage Specification
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Chipset DMD Features
        1. 8.3.1.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
        2. 8.3.1.2 DLPA200 - DMD Micromirror Driver
        3. 8.3.1.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
        4. 8.3.1.4 DLP7000 - DLP 0.7 XGA 2xLVDS Type-A DMD
          1. 8.3.1.4.1 DLP7000 XGA Chip Set Interfaces
            1. 8.3.1.4.1.1 DLPC410 Interface Description
              1. 8.3.1.4.1.1.1 DLPC410 IO
              2. 8.3.1.4.1.1.2 Initialization
              3. 8.3.1.4.1.1.3 DMD Device Detection
              4. 8.3.1.4.1.1.4 Power Down
          2. 8.3.1.4.2 DLPC410 to DMD Interface
            1. 8.3.1.4.2.1 DLPC410 to DMD IO Description
            2. 8.3.1.4.2.2 Data Flow
          3. 8.3.1.4.3 DLPC410 to DLPA200 Interface
            1. 8.3.1.4.3.1 DLPA200 Operation
            2. 8.3.1.4.3.2 DLPC410 to DLPA200 IO Description
          4. 8.3.1.4.4 DLPA200 to DLP7000 Interface
            1. 8.3.1.4.4.1 DLPA200 to DLP7000 Interface Overview
        5. 8.3.1.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMD Operation
        1. 8.4.1.1 Single Block Mode
        2. 8.4.1.2 Dual Block Mode
        3. 8.4.1.3 Quad Block Mode
        4. 8.4.1.4 Global Mode
    5. 8.5 Optical Interface and System Image Quality Considerations
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation - Lumens Based (typically used for display applications)
      4. 8.6.4 Micromirror Array Temperature Calculation - Power Density Based
    7. 8.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Device Description
      3. 9.2.3 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 DMD Interface
        1. 11.1.3.1 Trace Length Matching
      4. 11.1.4 DLP7000 Decoupling
        1. 11.1.4.1 Decoupling Capacitors
      5. 11.1.5 VCC and VCC2
      6. 11.1.6 DMD Layout
      7. 11.1.7 DLPA200
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
      2. 12.1.2 器件标记
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.2 Typical Application

A typical embedded system application using the DLPC410 controller and DLP7000 is shown in Figure 19. In this configuration, the DLPC410 controller supports input from an FPGA. The FPGA sends low-level data to the controller, enabling the system to be highly optimized for low latency and high speed.

DLP7000 D4100_system_Block_Diag_XGA_update.gifFigure 19. DLPC410 and DLP7000 Embedded Example Block Diagram