ZHCSA87F August 2012 – June 2019 DLP7000
Figure 9 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the DLPC410 to allow best signal flow.
Two LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the DLPC410 (DVALID).
Output LVDS buses transfer data from the DLPC410 to the DLP7000. Output buses LVDS A and LVDS B are used as highlighted in Figure 9.